5.6: The Zero Charging Limit

As we saw in Part 3, charging-induced shifts in the energy levels of conductors can significantly complicate the calculation of IV characteristics. Equation (5.4.5) demonstrates that charging can be neglected if the quantum capacitance is much smaller than the electrostatic capacitance, i.e. \(C_{Q} \ll C_{ES}\). For example, in Equation (5.4.5), if \(C_{Q} \ll C_{ES}\) then the charging, \(\delta N \rightarrow 0\).

In the zero charging limit, Equation (5.5.1) reduces to

\[ U=-qV_{GS} \nonumber \]

i.e. in this limit the channel potential simply tracks the gate bias.

Thus, in the zero charging limit, we can determine the current directly from Equation (5.3.6), with the channel potential \(U=-qV_{GS}\).

The zero charging limit almost always holds for insulators and transistors in the OFF state because the density of states at the Fermi level is small in both these examples. Determining whether a transistor remains in the zero charging limit in the ON state requires a comparison of \(C_{Q}\) and \(C_{ES}\). Bulk devices very rarely operate within the zero charging limit in the ON state. But many small conductors contain relatively few states at the Fermi level even in the ON state, such that \(C_{Q} \ll C_{ES}\) even when significant channel current is flowing.

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