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As mentioned earlier Network ASICs can be developed in-house (custom ASICs) or be procured from several merchant silicon vendors. The ASIC chipsets may have specific target markets: Enterprise, hyperscalers, or Service Providers.
Handling ASIC revisions
Whether the ASICs are developed in-house or are from merchant silicon vendors, they need to be tested on boards subjected to network traffic loads.
Despite the best efforts of the ASIC designers doing their testing in simulation before the chip tapes out (is sent to the ASIC foundry for fabrication), it is possible that errors are detected during these on-board tests that will require a new revision of the ASIC, called a new "spin." Depending on the nature of the error, it sometimes can be corrected with a metal layer spin, or in the worst case, an all-layer spin which would come at considerable expense to redo the chip masks.
Integration into schedules
When preparing the project schedule, the project manager must make risk assessments of the number of prototype board design revisions (to be discussed later) as well as the number of prototype ASIC spins. These assessments can include such criteria as the past track record of the design team, an assessment of the technology risk (are many new features being added and are the new features described in newly published specifications).
Testing
In addition to specific function testing, there typically is a part of the network switch developer's System Quality Assurance lab that tests maximum configurations, such as all ports passing full traffic at maximum rated speed.
Process Lot/Corner Lot Testing
The semiconductor manufacturing process that produces the network ASICs can have variability. In order to assess whether these process variations could potentially impact one's design, it is useful to consider ordering corner lots of the ASICs from the ASIC manufacturer. Corner lots also go by the following names: process lots and skewed lots.
The semiconductor foundry will, upon request, make chip wafers that they purposely skew to different process corners by altering the doping of NMOS and PMOS devices for the purpose of this production process variation immunity testing. The five "corners" that are skewed have a two-letter designation, where the first letter refers to the NMOS device, and the second refers to the PMOS device. There are 5 corners:[1]
- FF (fast fast), meaning both the P and N devices are purposely skewed to the fast corner.
- SF (slow fast)
- SS (slow slow)
- FS (fast slow)
- TT (typical typical), i.e., normal process is used.
As the project manager, you may be involved in ordering the corner lot ASICs from the ASIC manufacturer and scheduling the placement of the corner lot parts on boards in conjunction with corner lot parts for other critical components and scheduling the testing activity. The timing would be not long after ASIC tape-out or before the ASIC is released to production.
In order to build these boards with the skewed components, one must exercise special care in tracking which parts come from which corner and have a willing, capable prototype board manufacturer to handle these special cases.
There should be money in the project for this activity. The testing resource is likely a signal integrity engineer.
References
- Understanding semiconductor Process Lots (Corner Lots). Accessed February 16, 2026. This article provides an excellent overview of corner lots.
4.4.1: Network ASICs is shared under a CC BY 4.0 license and was authored, remixed, and/or curated by LibreTexts.
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