Podcasts · The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations
The Hidden Economics Behind Chip Packaging
· 8:24 · S1 E34
Episode The Hidden Economics Behind Chip Packaging
In Episode 34, Lucas and Luna unpack a quiet revolution that rarely makes headlines: advanced chip packaging. While everyone obsesses over transistor shrinks, the way chips get physically assembled is becoming a bottleneck and an opportunity. Lucas explains why TSMC's CoWoS packaging is suddenly critical for AI accelerators, how Intel is betting on Foveros, and why the cost per extra millimeter of silicon interposer can run into millions. Luna asks whether the packaging renaissance means old fabs can stay relevant. They also explore how substrate shortages—yes, the board underneath—are delaying high-end chips for months. Specific examples: NVIDIA's H100 supply constraints, Apple's UltraFusion packaging for M-series, and the $3 billion Samsung is investing in panel-level packaging. A clear look at the layer of hardware engineering most people overlook.
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Transcript
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