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Course10610516163 lectures

VLSI Physical Design

Prof. Indranil Sengupta · IIT Kharagpur

Start with lecture 1 At NPTEL

Lectures

Week 1

  1. Lecture 1: Introduction Video
  2. Lecture 2: Design Representation Video
  3. Lecture 3: VLSI Design Styles (Part 1) Video
  4. Lecture 4: VLSI Design Styles (Part 2) Video
  5. Lecture 5: VLSI Physical Design Automation (Part 1) Video
  6. Lecture 6: VLSI Physical Design Automation (Part 2) Video

Week 2

  1. Lecture 7: Partitioning Video
  2. Lecture 8: Floorplanning Video
  3. Lecture 9: "Floorplanning Algorithms Video
  4. Lecture 10: Pin Assignment Video
  5. Lecture 11: Placement (Part 1) Video
  6. Lecture 12: Placement (Part 2) Video
  7. Lecture 13: Placement (Part 3) Video
  8. Lecture 14: Placement (Part 4) Video

Week 3

  1. Lecture 15: Grid Routing (Part 1) Video
  2. Lecture 16: Grid Routing (Part 2) Video
  3. Lecture 17: Grid Routing (Part 3) Video
  4. Lecture 18: Global Routing (Part 1) Video
  5. Lecture 19: Global Routing (Part 2) Video

Week 4

  1. Lecture 20 : Detailed Routing (Part 1) Video
  2. Lecture 22: Detailed Routing (Part 3) Video
  3. Lecture 24 : Clock Design (Part 1) Video
  4. Lecture 25 : Clock Design (Part 2) Video
  5. Lecture 26 : Clock Design (Part 3) Video

Week 5

  1. Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1) Video
  2. Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2) Video
  3. Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3) Video
  4. Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4) Video
  5. Lecture 31: POWER AND GROUND ROUTING Video

Week 6

  1. Lecture 32: Time Closure (Part 1) Video
  2. Lecture 33: Time Closure (Part 2) Video
  3. Lecture 34: Time Closure (Part 3) Video
  4. Lecture 35: Time Closure (Part 4) Video
  5. Lecture 36: Time Closure (Part 5) Video
  6. Lecture 37: Timing Driven Placement Video

Week 7

  1. Lecture 38: Timing Driven Routing Video
  2. Lecture 39: Physical Synthesis (Part 1) Video
  3. Lecture 40 : Physical Synthesis (Part 2) Video
  4. Lecture 41: Performance-Driven Design Flow Video
  5. Lecture 42 : Miscellaneous Approaches to Timing Optimization Video

Week 8

  1. Lecture 43 :Interconnect Modeling (Part 1) Video
  2. Lecture 44 : Interconnect Modeling (Part 2) Video
  3. Lecture 45 : Design Rule Check Video
  4. Lecture 46 : Layout Compaction (Part 1) Video
  5. Lecture 47 : Layout Compaction (Part 2) Video

Week 9

  1. Lecture 48 : Testing of VLSI Circuits Video
  2. Lecture 49 : Fault Modeling (Part 1) Video
  3. Lecture 50 : Fault Modeling (Part 2) Video
  4. Lecture 51: Fault Simulation (Part 1) Video
  5. Lecture 52 : Fault Simulation (Part 2) Video

Week 10

  1. Lecture 53 : Test Pattern Generation Video
  2. Lecture 54: Design for Testability Video
  3. Lecture 55: Boundary Scan Standard Video
  4. Lecture 56: Built-in Self-Test (Part 1) Video
  5. Lecture 57: Built-in Self-Test (Part 2) Video

Week 11

  1. Lecture 58 : Low Power VLSI Design Video
  2. Lecture 59 : Techniques to Reduce Power Video
  3. Lecture 60 : Gate Level Design for Low Power (Part 1) Video
  4. Lecture 61 : Gate Level Design for Low Power (Part 2) Video

Week 12

  1. Lecture 62 : Other Low Power Design Techniques Video
  2. Lecture 63 : Algorithmic Level Techniques for Low Power Design Video
  3. Lecture 64 : Summarization of the Course Video

Live Session

  1. Live Session 12-03-2020 Video

Syllabus and materials

At NPTEL, as the course publishes them.

Credits and licence

Institution
IIT Kharagpur
Department
Computer Science and Engineering
Teacher
Prof. Indranil Sengupta
Level
Undergraduate
Language
English
Subjects
Computer science, Engineering
Source
NPTEL
Licence
CC BY-NC-SA, as NPTEL states it. Non-commercial use only. NPTEL's terms
Attribution
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