FastIC+, an 8-channel front-end ASIC in 65 nm CMOS for the readout of photosensors with intrinsic gain

About

Achieving picosecond-level timing in large-scale detector systems requires front-end electronics that combine excellent time resolution with low power consumption and full integration. In this seminar we present FastIC+, an 8-channel front-end ASIC in 65 nm CMOS for the readout of photosensors with intrinsic gain (SiPMs, PMTs, MCPs), which provides on-chip digitization of both arrival time and energy at 12.5 mW per channel.

We will describe the architecture of the chip, including the current-mode input stage capable of handling both signal polarities, the parallel time, energy and trigger branches, and the Time-to-Digital Converter based on a PLL generating 16 phases at 1.28 GHz, yielding a 24.4 ps time bin. We will then review the experimental characterization: a single-photon time resolution of (98 ± 1) ps FWHM with 3×3 mm² SiPMs, and coincidence time resolutions of (85 ± 1) ps FWHM with 2×2×3 mm³ LGSO crystals and (130 ± 1) ps FWHM with 2.8×2.8×20 mm³ LYSO:Ce,Ca — to our knowledge the first sub-100 ps CTR reported with on-chip digitization. Comparisons between analog and digital readout modes demonstrate that the internal TDC contributes negligibly to the overall timing budget, which remains dominated by sensor jitter.

Finally, we will discuss how this development, which began within the framework of CERN medical applications, has had an impact into other domains. In particular, it led to the design of the FastRICH chip, developed for the sensor readout of the LHCb RICH detector, which will become the first RICH detector with timing capability, while the FastIC family continues to find broad dissemination in other fields, most notably in time-of-flight PET instrumentation and mass spectrometry.

Coffee will be served at 10:30

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