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A Multigigabit Link Layer Protocol for Single Picosecond Latency Determinism Using AMD Ultrascale+ GTH and GTY Transceivers

Paul Bachek · CERN

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About

Precision timing distribution systems require deterministic and repeatable high speed serial data link latency. The EIC Timing Data Link will employ a specialized link layer protocol for deterministic multigigabit communication using AMD Ultrascale+ GTH and GTY transceivers. Link latency must also be measurable to accurately compensate in real time for latency variations of the physical medium. The point-to-point link is full duplex and fully synchronous with a latency control algorithm to align the internal clocks of each system with picosecond resolution. Deterministic clock domain crossing between systems is ensured using static timing analysis of the elastic buffer control signals.

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The talk

  1. A Multigigabit Link Layer Protocol for Single Picosecond Latency Determinism Using AMD Ultrascale+ GTH and GTY Transceivers 2026-05-29 · 25 min · CERN's player

Credits and licence

Institution
CERN
Speaker
Paul Bachek
Year
2026
Language
English
Source
CERN
Licence
CERN, as CERN states it. CERN's terms
Attribution
© CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
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