Recovered Clock Phase Monitoring on AMD Transceivers for Deterministic Timing

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After the Phase-II upgrade of the Large Hadron Collider at CERN, pile-up discrimination in the CMS Electromagnetic Barrel Calorimeter demands a clock system with picosecond precision and deterministic phase. Although modern electronics can achieve sub-5 ps RMS jitter, widely used FPGAs do not ensure phase repeatability after reset. Their Multi-Gigabit Transceivers prioritize bit error rate robustness over deterministic recovered clock phase. Measurements with the Barrel Calorimeter Processor (BCP-V2) show that MGT resets can yield two discrete recovered clock phases about 10 ps apart, while the internal Delay Aligner adds temperature-dependent drift. The BCP-V2 integrates a picosecond-resolution monitor achitecture that extracts the clock before the Delay Aligner and the FPGA fabric (RXRECCLKOUT) and compares it to RXUSRCLK, typically used as the LHC reference, using a Digital Dual Mixer Time Difference method, enabling real-time detection of clock phase jumps and drifts.

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