About
This talk demonstrates that adopting DevOps principles for FPGA projects is neither complex nor prohibitively expensive. Using widely available open-source tools, mature software-style pipelines can be applied to hardware design with meaningful productivity gains.
The presentation will cover a practical end-to-end approach, including: - Effective use of Git-based version control for HDL, constraints, IP cores, and testbenches - Automated CI pipelines for synthesis, place-and-route, and bitstream generation - Testing via simulation - Hardware-in-the-loop (HIL) validation using FPGA boards with CI runners - Automated firmware loading, test execution, and result reporting for closed-loop verification
The talk concludes with a concrete industrial case study: the ASIC prototyping phase of an edge AI audio processing device.
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The talk
Credits and licence
- Institution
- CERN
- Speaker
- Matteo Vit
- Year
- 2026
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed