About
The Dynamic Derandomizing Buffer is a firmware design for joining time-stamped packets form multiple incoming data streams with randomly varying time-skews into a single time-ordered output stream. It is developed at CERN primarily to handle the output from the novel FastRICH ASIC (the LHCb RICH detector readout chip for Runs 4 and 5), but intentionally made agnostic to this use-case so it can be used in any similar real-time stream processing scenario. Written in pure VHDL, it is also fully portable: it was successfully built for both Intel and AMD devices.
This presentation covers a scalable and configurable tree-based aggregation architecture, portable BRAM-based buffering components, and a special time-stamp windowing algorithm which guides the time-ordering process. We also share our experience in applying test-driven development approach (using formal verification and self-testing UVVM-based simulation) to a complex FPGA design.
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The talk
Credits and licence
- Institution
- CERN
- Speaker
- Mitja Vodnik
- Year
- 2026
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed