About
High-performance computing and data-intensive infrastructures are increasingly limited by data movement rather than processing power. Large scientific experiments such as those at CERN, together with AI training clusters and datacenters, generate continuous data streams that must be handled at multi-100 Gb/s under strict latency, power, and storage constraints. Lossless compression in FPGA or ASIC hardware reduces bandwidth and memory needs without altering scientific results, precision, or training accuracy. This presentation examines hardware architectures for lossless compression in HPC, AI, datacenter, and scientific data acquisition systems. Emphasis is on deterministic-latency pipelines operating inline with Ethernet, PCIe, high-bandwidth memory, and storage. Algorithms including LZ4, Snappy, GZIP/DEFLATE/Zlib, and Zstandard are compared in terms of ratio, resource cost, and throughput, highlighting the trade-off between ultra-low-latency cores and higher-ratio formats.
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The talk
Credits and licence
- Institution
- CERN
- Speaker
- Calliope-Louisa Sotiropoulou
- Year
- 2026
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed