About
HDL simulation is essential for verifying digital designs, but its computational intensity often results in slow turnaround times, delaying development cycles. This presentation demonstrates how AMD Alveo FPGA acceleration cards, integrated with open source HDL simulators and frameworks, can dramatically speed up simulation workflows.
The presentation begins by outlining the bottlenecks in traditional HDL simulation and the potential of FPGA-based acceleration. Next, I present the methodology, focusing on the integration of Alveo cards with open source tools, and share practical insights into setup, optimization, and common pitfalls. Finally, I showcase performance benchmarks and real-world use cases, outlining additional benefits of using co-simulation besides the expected performance increase.
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The talk
Credits and licence
- Institution
- CERN
- Speaker
- Matthias Kern
- Year
- 2026
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed