About
This talk takes an in-depth look inside a UVVM VVC, explaining its internal architecture and core design principles. Key concepts such as the command-based interface, command queue, command interpreter, and executor are explored in detail, along with synchronization mechanisms, transaction handling, and the interaction with Bus Functional Models (BFMs).
Building on this foundation, the presentation demonstrates how to develop custom UVVM-compliant VVCs using the official templates and generator support. Practical guidance and best practices are shared to help attendees design reusable, maintainable, and well-integrated verification components that fit seamlessly into existing UVVM-based testbenches.
The talk is aimed at FPGA developers who are already familiar with the basics of UVVM and want to move beyond using existing VVCs—gaining the confidence to understand, extend, and create their own verification components.
00:00:00 Slide 1
00:00:23 Slide 2
00:01:24 Slide 3
00:01:47 Slide 4
00:02:24 Slide 5
00:03:37 Slide 6
00:04:21 Slide 7
00:05:22 Slide 8
00:06:40 Slide 9
The talk
Credits and licence
- Institution
- CERN
- Speaker
- Markus Leiter
- Year
- 2026
- Language
- English
- Subjects
- Art, architecture and design
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed