About
High-precision time measurements on the order of picoseconds ($10^{-12}$), as required in fluorescence lifetime microscopy and time-of-flight (ToF) applications, can be achieved using Time-to-Digital Converters (TDCs). Traditional timing methods rely on high-frequency clock counters, which become impractical for such small time intervals. A solution is to exploit the hardware of FPGAs to achieve sub-clock time resolutions. Although much of the existing literature on TDCs focuses on minimizing resolution while maintaining accuracy, the linearity and temperature dependence on performance is often overlooked. These factors are strongly tied to the underlying fabrication technology and hardware architecture. This presentation explores a Tapped-Delay-Line (TDL) TDC design implemented across different FPGA families (AMD, Efinix, Intel), with an emphasis on their linearity and temperature dependency, highlighting the performance differences and considerations for practical applications..
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The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- Gian-Luca Brazerol
- Year
- 2025
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed