About
As modern digital systems demand increasingly higher data rates, the role of high-throughput, low-latency communication becomes critical in applications such as data acquisition, real-time processing, and high-performance computing. This talk describes how UDPIP and TCPIP hardware protocol stack IP cores can be designed to deliver deterministic, line-rate Ethernet communication in FPGA-based systems. We discuss the architectural design and implementation approaches that enable these cores to achieve high performance while maintaining efficient FPGA resource usage.
Through test results and integration examples, we demonstrate how IP cores such as these can be effectively deployed in complex system designs requiring scalable and reliable networking solutions. Practical aspects such as interoperability, configurability, and system-level integration are also addressed, providing attendees with actionable insights into leveraging hardware-accelerated networking for demanding, data-driven applications..
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The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- Calliope-Louisa Sotiropoulou
- Year
- 2025
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed