About
The Electron Ion Collider (EIC) Timing Data Link requires high precision clock recovery for accelerator master clock distribution. To meet the performance requirements a novel method for extracting a low jitter data frame clock from serial encoded data using Xilinx Ultrascale+ transceivers is presented. The frame clock frequency is at the word rate of the serial data link and its phase is deterministic. Dedicated FPGA output pins are used to eliminate phase drift from routing variations and minimize the effects of process, voltage, and temperature (PVT). This method enables timing endpoints to recover the accelerator master clock with minimal added phase noise..
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The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- Paul Bachek
- Year
- 2025
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed