About
AXI4 (Memory-Mapped, Stream) is a well established set of flexible bus interfaces. They can support various address and/or data widths, have optional support for bursts, byte strobing, back-pressure, sideband signals, etc.
Writing generic yet easily maintainable AXI-compatible modules is hard: implementation must take care of abiding interoperability rules for optional signals at all times. Using generics and relying on default port values is root for a code maintenance nightmare, if even possible at all.
Using standard VHDL-93 constructs, We propose an approach for modelling interfaces and configuration in an abstract manner in a way it guarantees correct protocol encoding/decoding with enhanced code compactness, clarity and genericity, still producing optimal synthesis results.
Method, applied to AXI4, will be described in depth. Application of the method to other classes of modelling problems will be discussed.
Reusable library will be available under MIT license..
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The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- Nicolas Pouillon
- Year
- 2025
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed