About
HDLRegression was developed to provide a reliable, efficient tool for regression testing of maintenance testbenches for UVVM and other FPGA project testbenches. It simplifies simulations with minimal changes—just a single comment in the testbench entity—making it easy to integrate into existing projects.
One big advantage is its independence from any specific verification framework, enabling use with UVVM, OSVVM, VUnit, or any other in-house tools for maximum flexibility.
As FPGA designs grow more complex, numerous tests are needed to verify functionality. HDLRegression addresses this with efficient, customisable test execution and a structured testing environment where results are easily accessible.
By offering reliable and efficient regression testing, HDLRegression improves testing processes, reduces complexity, and increases reliability in FPGA projects..
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The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- Marius Elvegård
- Year
- 2025
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed