About
Chisel4ml is a tool we developed for generating fast implementations of deeply quantized neural networks to FPGA devices. The tool is implemented in the Chisel Hardware Construction Language, and has a frontend in Python, to enable interfacing with neural network training libraries. We will present basics of the Chisel language and compare chisel4ml against hls4ml. In general, chisel4ml, is able to generate the hardware much faster then high-level synthesis solutions, because it uses structural descriptions of the circuits..
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The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- Jure Vreča
- Year
- 2025
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed