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Talk22 min

Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.

Gianmario Bergamin · CERN

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About

The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This contribution presents customized Design for Testability methods to replace the currently used functional tests that show limited coverage and long testing time. Scan-chain design, memory and Logic Built-In-Self-Test have been adapted for radiation-hard ASICs and introduced on-chip for a novel testing approach. Design flow and implementation choices will be presented together with silicon results..

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The talk

  1. Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC. 2021-09-22 · 22 min · CERN's player

Credits and licence

Institution
CERN
Department
Conferences
Speaker
Gianmario Bergamin
Year
2021
Language
English
Subjects
Physics, Engineering
Source
CERN
Licence
CERN, as CERN states it. CERN's terms
Attribution
© CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
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