About
The development, testing and operation of FPGA algorithms require the implementation of flexible and efficient real-time monitoring. This can be achieved via the insertion of dedicated buffers between the logical blocks of the FPGA firmware. These buffers are implemented in the firmware to spy the dataflow between the internal blocks (Spybuffers). They must provide configurable size and are equipped with a playback feature that allows to inject simulated data into the firmware path. A dedicated control software sets the Spybuffer mode (monitoring or playback), performs memory readout and analyses the results. In this talk we discuss the SpyBuffer design for monitoring and playback operations, the interface of the SpyBuffer with the AXI Chip to Chip interface, as well as the software layer to control the SpyBuffers and their operating modes. 1.
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The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- Iacopo Longarini
- Year
- 2024
- Language
- English
- Subjects
- Computer science
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed