About
An implementation of an ultra-low latency BDT fully evaluated on an FPGA was introduced for 2024 data taking in the ATLAS experiment with inference latency of 60 ns at 200 MHz and full pipelining. The BDT model is synthesized using Conifer and integrated into existing firmware written in VHDL. I will discuss some technical details on how I transferred HLS-generated code into existing firmware. For example, as the BDT is auto-generated, the signal delays must be adjusted at each retraining of the model, which is not practical to do manually. I'll show how I tackled this issue by implementing a python package to automatically compute sums and delays of signals..
0:00:00 Slide 1
0:02:08 Slide 2
0:03:49 Slide 3
0:06:03 Slide 4
0:10:43 Slide 5
0:12:22 Slide 6
0:13:51 Slide 7
0:14:59 Slide 8
0:19:00 Slide 9
0:22:50 Slide 10
The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- David Reikher
- Year
- 2024
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed