About
Firmware design is a major challenge in LHC experiment upgrades, often leading to significant project delays. While non configurable systems were immediately operational, recent experiences show firmware and hardware readiness can take years. This underscores the need for innovative methods to speed up firmware design and deployment. This study utilizes advanced firmware design techniques, like High-Level Synthesis (HLS), for the ATLAS Liquid Argon Calorimeter trigger processor. HLS simplifies the design process by focusing on essential functions rather than intricate hardware details such as clock networks or signal interfaces. This method allows for easy trade-offs between latency and area, essential for optimizing firmware performance. It enhances firmware maintenance, latency, logic area usage, and timing accuracy. The HLS application has the potential to streamline firmware design, reducing project delays, and increasing efficiency in large-scale experiments like the LHC upgrades..
0:00:00 Slide 1
0:02:21 Slide 2
0:03:24 Slide 3
0:04:48 Slide 4
0:06:23 Slide 5
0:07:46 Slide 6
0:08:59 Slide 7
The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Taught by
- Melissa Aguiar, Marcos Vinicius Silva Oliveira, Lucca Oliveira Facio Viccini
- Year
- 2024
- Language
- English
- Subjects
- Art, architecture and design
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Tweens profiles and older, judged from what the source says about it. How courses are placed