About
RISC-V is a fully open source processor architecture. It's rapidly being adopted by major tech companies as an alternative to ARM licenses. With the advent of the IceStorm toolchain for the Lattice iCE40 FPGA, it's now possible to construct your own RISC-V processor core and compile code to run on it using exclusively open source tools. This talk will include an overview of the RISC-V architecture, the toolchains for device synthesis and code compilation and will end with a very short demo of a working processor built during the talk!.
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The talk
Credits and licence
- Institution
- CERN
- Department
- IT Lightning Talks (ITLT)
- Speaker
- James Devine
- Year
- 2019
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed