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Talk1 h 12 min

Directions in parallel processor architecture, and GPUs too

Olivier Giroux · CERN

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About

Modern computing is power-limited in every domain of computing. Performance increments extracted from instruction-level parallelism (ILP) are no longer power-efficient; they haven't been for some time. Thread-level parallelism (TLP) is a more easily exploited form of parallelism, at the expense of programmer effort to expose it in the program. In this talk, I will introduce you to disparate topics in parallel processor architecture that will impact programming models (and you) in both the near and far future.

About the speaker

Olivier is a senior GPU (SM) architect at NVIDIA and an active participant in the concurrency working group of the ISO C++ committee. He has also worked on very large diesel engines as a mechanical engineer, and taught at McGill University (Canada) as a faculty instructor. .

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The talk

  1. Directions in parallel processor architecture, and GPUs too 2014-06-27 · 1 h 12 min · CERN's player

Credits and licence

Institution
CERN
Department
Computing Seminar
Speaker
Olivier Giroux
Year
2014
Language
English
Subjects
Computer science
Source
CERN
Licence
CERN, as CERN states it. CERN's terms
Attribution
© CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
Who can watch
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