About
Advancements in design automation technologies, such as high-level synthesis (HLS), have raised the input abstraction level and made the design entry process for FPGAs more friendly to software programmers. In contrast, the backend compilation process for implementing designs on FPGAs is considerably more lengthy compared to software compilation. While software code compilation may take just a few seconds, FPGA compilation times can often span from several minutes to hours due to the complexity of the underlying toolchain and the ever-growing device capacity. In this presentation, we provide an overview of the current advancements in fast compilation techniques for FPGAs. Furthermore, We present a very fast compilation methodology that generates in a matter of seconds placed-and-routed kernel designs for AMD FPGAs. This approach accelerates the C-to-FPGA implementation process by up to 33x with only 0.9x of degradation in Fmax compared to a conventional implementation flow..
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The talk
Credits and licence
- Institution
- CERN
- Department
- FPGA Developers' Forum (FDF)
- Speaker
- Andrea Guerrieri
- Year
- 2024
- Language
- English
- Source
- CERN
- Licence
- CERN, as CERN states it. CERN's terms
- Attribution
- © CERN. CERN provides its audiovisual media free of charge for educational and informational use, credited to CERN; this lecture is shown in CERN's own player.
- Who can watch
- CERN gives no rating. Invisible Network shows it to Teens profiles and older, judged from what the source says about it. How courses are placed