# How On-Chip MRAM Is Merging Memory and Storage

An episode of [The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations](https://invisiblenetwork.ai/podcast/1896799982), 27 Jul 2026, 8:16.

Audio: https://audio.fexingo.com/business/the-hardware-podcast/episode-0134.mp3

On-chip MRAM is emerging as a game-changing embedded memory technology that combines the speed of SRAM with the non-volatility of Flash. In this episode, Lucas and Luna explore how magnetoresistive RAM is being integrated directly into processors to create unified memory architectures. They discuss a specific example: Everspin's 28nm STT-MRAM, which achieves sub-nanosecond write times and virtually unlimited endurance. By replacing both cache and storage tiers on a single chip, MRAM cuts power consumption by up to 70% in IoT and edge AI devices. The hosts examine the physics behind the magnetic tunnel junction, the scaling challenges, and why foundries like TSMC and Samsung are racing to commercialize embedded MRAM. They also touch on the implications for data center memory disaggregation and next-generation wearables. If you are a hardware engineer or just curious about how chips are evolving, this episode offers a clear, detailed look at a technology that could reshape the memory hierarchy. #EmbeddedMRAM #STTMRAM #Everspin #TSMC #Samsung #NonVolatileMemory #UnifiedMemory #CacheHierarchy #StorageClassMemory #IoTDevices #EdgeAI #MagneticTunnelJunction #SpinTransferTorque #OnChipMemory #HardwarePodcast #FexingoBusiness #BusinessPodcast #Technology Keep every episode free: buymeacoffee.com/fexingo

## Transcript

Lucas: The gap between cache latency and storage latency is about six orders of magnitude — microseconds versus milliseconds. On-chip MRAM is starting to shrink that gap, and it could fundamentally change how we design processors.
Luna: MRAM — magnetoresistive RAM. I've seen it in some microcontroller datasheets, but is it actually ready to replace both SRAM and Flash on the same die?
Lucas: That's exactly what's happening. Everspin has been shipping discrete stt mram for years, but now they've got a 28-nanometer embedded MRAM process that achieves sub-nanosecond write times and virtually unlimited endurance. TSMC and Samsung are both offering embedded MRAM as a standard option in their 28-nanometer and 22-nanometer nodes.
Luna: Sub-nanosecond write — that puts it in SRAM territory. But SRAM is volatile and uses six transistors per bit. MRAM uses one transistor and one magnetic tunnel junction. The density advantage must be huge.
Lucas: Exactly. A typical SRAM cell takes about 140 square femtometers in 28-nanometer, while an MRAM cell is around 40 square femtometers — more than three times denser. And because it's non-volatile, you can power down blocks completely without losing data. That's a game-changer for battery-powered devices.
Luna: So you could have a single chip that holds the processor cache, the main memory, and even the file system, all in one uniform memory space? That sounds like the holy grail of memory hierarchy.
Lucas: Right. And several companies are already doing it. For example, in 2025, a company called Ferroelectric Memory Co. demonstrated a risc v SoC with embedded MRAM replacing both L2 cache and external Flash. The chip consumed about 70 percent less power than a comparable sram plus flash design. But there's a catch — write energy is still higher than SRAM for the first write, though subsequent writes are comparable.
Luna: Higher write energy — that matters for applications that write frequently, like data logging or AI training. But for read-heavy workloads like inference, it's ideal.
Lucas: Precisely. And the endurance is stellar — Everspin quotes 10 to the 14 cycles, which is effectively unlimited compared to Flash's 10 to the 5 or 6. That makes it suitable for code storage that's updated over-the-air, or for wear-leveling systems that rewrite constantly.
Luna: I want to dig into the physics a bit. The magnetic tunnel junction — it's a stack of ferromagnetic layers separated by an oxide barrier. The resistance changes depending on the magnetization direction. That's the 'tunnel magnetoresistance' effect, right?
Lucas: Yes. In stt mram, a spin-polarized current directly switches the free layer. No external magnetic field needed. That's what enables the small cell size and the fast write. But there's a scaling problem: as the MTJ shrinks below 20 nanometers, the thermal stability factor drops, meaning the bit can flip accidentally from thermal noise. So foundries are exploring new materials like perpendicular magnetic anisotropy and novel barrier layers.
Luna: Thermal stability — that's the trade-off between retention and speed. For cache applications, you might only need milliseconds of retention, so you can tolerate lower stability. For storage, you need years. So you can tune the MTJ design for the target application.
Lucas: Exactly. And some designers are already doing that. They'll use a small, fast MRAM array for L2 cache and a larger, more stable array for main memory — all on the same chip. The foundry provides different MTJ 'flavors' for different retention targets.
Luna: Speaking of foundries — TSMC's eMRAM on 22-nanometer is in production for automotive microcontrollers. Samsung has a 28-nanometer fd soi eMRAM for IoT. And GlobalFoundries offers it on 22FDX. It's becoming a mainstream option.
Lucas: And it's not just microcontrollers. Data center architects are looking at MRAM for disaggregated memory pools. Because it's non-volatile and fast, you can build a memory module that persists through power cycles without battery backup. That saves space and improves reliability.
Luna: But let's be honest — MRAM still hasn't displaced DRAM in servers. The density isn't there yet. The most dense MRAM chips are about 1 gigabit, while DRAM is at 16 gigabit. But for embedded applications, the integration benefit outweighs the density gap.
Lucas: Right. And the roadmaps show MRAM scaling to 5-nanometer by 2028, using new switching mechanisms like spin-orbit torque. That could enable densities comparable to DRAM. But that's a few years out.
Luna: We talk a lot about how chips are getting smarter, but how they remember is just as important. MRAM is one of those quiet revolutions that might end up in every device you own.
Lucas: You know, Luna, it's conversations like this that remind me why we do this show. We don't run ads — we just dig into the tech that matters. If this episode gave you something useful, and you want to support that kind of in-depth hardware talk, you can find us at buy me a coffee dot com slash fexingo. It's a simple way to keep the show ad-free and focused.
Luna: Yeah. No sponsors means no filler. Just the signal. If you like that, the link is there. And we appreciate every single person who chips in.
Lucas: Absolutely. Now, back to the tech — one of the most interesting applications I've seen is in space electronics. Rad-hard MRAM is being used in satellites because it's immune to single-event upsets that plague SRAM. NASA's Jet Propulsion Lab has been testing MRAM for Mars rovers.
Luna: Radiation tolerance — that's another big advantage. MRAM stores data magnetically, not as charge, so ionizing radiation doesn't flip the bits. That's huge for any environment with high radiation: space, nuclear plants, even particle accelerators.
Lucas: And for medical implants, the non-volatility means the device can retain calibration data even when the battery runs out. There's a pacemaker design using embedded MRAM that stores patient history right on the chip.
Luna: Let's talk about the cost side. MRAM adds extra mask layers — typically three to five more than a standard CMOS flow. That pushes up wafer cost. But for SoCs that would otherwise need separate SRAM and Flash dies, the system-level cost can be lower.
Lucas: Exactly. You save on packaging, board space, and power delivery. And because MRAM is so fast, you can eliminate the need for a separate cache SRAM, which is often a big die area. So the total silicon area might actually shrink.
Luna: I think the next big milestone will be when a major application processor — like a phone chip — integrates MRAM for the last-level cache. That would really prove the technology.
Lucas: Qualcomm and MediaTek are both rumored to be evaluating eMRAM for their 3-nanometer chipset designs. If that pans out, we could see MRAM in flagship phones by 2028. The era of unified memory might finally be here.
Luna: To keep the hardware conversation going, we'll be watching the IEEE International Memory Workshop later this year. The papers on MRAM are always the most talked-about.
Lucas: Same. And if you are watching too, drop us a note. We love hearing from listeners who are building with this stuff. Until next time, keep your bits non-volatile.
Luna: And your tunnel junctions stable. See you next week.

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