# Why Chip Designers Are Embracing Heterogeneous Integration

An episode of [The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations](https://invisiblenetwork.ai/podcast/1896799982), 15 Jun 2026, 9:50.

Audio: https://audio.fexingo.com/business/the-hardware-podcast/episode-0053.mp3

On today's Hardware Podcast, Lucas and Luna explore heterogeneous integration — the chip design strategy that stacks silicon, III-V compounds, and photonics into a single package. They break down how this approach enabled AMD's MI300X AI accelerator, which combines nine chiplets on a single interposer to rival NVIDIA's flagship GPU. The hosts discuss the technical challenges of mixing different process nodes, the role of TSMC's CoWoS-L packaging, and why heterogeneous integration is becoming essential as Moore's Law slows. Listeners will learn how this technique cuts costs, improves performance, and why every major chipmaker is racing to adopt it. #HeterogeneousIntegration #AMD #MI300X #Chiplets #AdvancedPackaging #TSMC #CoWoS #MooresLaw #AIChips #Semiconductors #GPU #NVIDIA #III-V #SiliconPhotonics #Technology #Hardware #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo

## Transcript

Lucas: If you've been following the AI chip race, you've heard the phrase 'heterogeneous integration' thrown around a lot. But what does it actually mean, and why is it suddenly everywhere?
Luna: I've seen it in press releases from AMD, Intel, even NVIDIA. But I'll admit, I wasn't totally clear on the distinction from just 'advanced packaging.'
Lucas: Right, and that confusion is fair because heterogeneous integration is a subset of advanced packaging, but it's a specific philosophy. The basic idea: instead of building one monolithic chip on a single process node, you take smaller dies — chiplets — made on different process technologies, and you package them together so they work as one.
Luna: Different process technologies — meaning you might have a logic chiplet on a leading-edge node, but memory or analog on older, cheaper nodes?
Lucas: Exactly. And that's the key economic driver. Making everything on the latest 3-nanometer node is astronomically expensive. A single mask set at 3nm can cost over $30 million. So if you can put your compute chiplets on 3nm but your I/O and memory controllers on 5nm or 7nm, you save huge amounts of money.
Luna: But is it just about cost? Or are there performance benefits too?
Lucas: Both. Let me give you a concrete example: AMD's MI300X, the AI accelerator they launched last year. That part uses nine chiplets — that's right, nine — on a single interposer. Three compute dies with Zen 4 cores and CDNA 3 graphics engines, plus six memory dies for HBM3. The compute dies are on 5nm, the memory on a different node. And it's all stitched together with TSMC's CoWoS-L packaging.
Luna: CoWoS — that's 'chip-on-wafer-on-substrate,' right?
Lucas: Right. And the 'L' variant adds a silicon bridge for higher-density interconnects. The result is a single package with 192 gigabytes of memory and 1.3 terabytes per second of bandwidth. That's competitive with NVIDIA's H100, but AMD was able to get there faster and cheaper by reusing existing chiplet designs rather than building a massive monolithic GPU.
Luna: So heterogeneous integration is basically the reason AMD can compete with NVIDIA in AI despite having a smaller R&D budget.
Lucas: It's a big part of it. And it's not just AI. The same approach is showing up in everything from smartphone processors to networking chips. Qualcomm's Snapdragon 8 Gen 3 uses chiplets for the modem and application processor. Even Apple's M-series chips integrate multiple dies — though they're more homogeneous in process node.
Luna: But there must be downsides. You're connecting dies across a package — that introduces latency, power overhead, and reliability concerns.
Lucas: Absolutely. The interconnects between chiplets are slower than on-die wires. So you need very fast die to die interfaces. Standards like UCIe — Universal Chiplet Interconnect Express — are emerging to address that. The physical layer has to handle things like retiming, ECC, and thermal expansion mismatches.
Luna: Thermal expansion — because the chiplets might be made of different materials? Silicon versus maybe gallium nitride or something?
Lucas: Exactly. And that's where the 'heterogeneous' really comes in. You can envision a package that combines a silicon CMOS logic chiplet with a gallium arsenide RF chiplet for 5G, or a silicon photonics chiplet for optical I/O. Each material has different thermal and electrical properties. Getting them to work together reliably is a massive engineering challenge.
Luna: Which is why TSMC and Intel are investing billions in advanced packaging fabs. They're not just selling silicon anymore; they're selling integration services.
Lucas: Right. And the economics are shifting. For decades, the semiconductor industry was about shrinking transistors. Now, the differentiation is increasingly in how you package them. Gordon Moore himself predicted that packaging would become the performance bottleneck — and he was right.
Luna: If today's conversation gave you something useful, you know, the way this show stays ad-free is through listener support. People can help keep it going at buy me a coffee dot com slash fexingo.
Lucas: Yeah, it really does make a difference. And we appreciate everyone who chips in. So back to the technical side: one of the most interesting recent developments is Intel's Foveros technology, which stacks chiplets vertically rather than side by side. That saves footprint and can reduce latency.
Luna: Right, because with side-by-side on an interposer, you're limited by the reticle size of the lithography tool — you can't make an interposer bigger than about 27 by 27 millimeters without stitching.
Lucas: Exactly. So vertical stacking lets you pack more compute into the same area. Intel's Meteor Lake processors use Foveros to stack a compute tile on top of a base tile. But it introduces thermal challenges — the bottom die has to handle the heat from the top die.
Luna: And that's why thermal interface materials are so critical, which we covered in episode 33. But I want to zoom out: is heterogeneous integration the new Moore's Law? Is that the narrative?
Lucas: It's part of what some people call 'More than Moore' — the idea that we'll get performance gains not just from smaller transistors but from smarter packaging and specialization. Heterogeneous integration lets you mix analog, digital, RF, and photonics in ways that would be impossible on a single monolithic chip. So yes, it's a key lever.
Luna: Speaking of photonics — that's a frontier where heterogeneous integration really shines. Silicon photonics chiplets can be bonded directly to CMOS logic, enabling high-speed optical interconnects right at the processor edge.
Lucas: And we're already seeing that in data centers. Companies like Ayar Labs are developing optical I/O chiplets that replace electrical SerDes, cutting power consumption by an order of magnitude. Those chiplets are built on a different process — typically indium phosphide — and then integrated with a silicon logic die.
Luna: So the trend is clear: the chip of the future isn't a single slab of silicon; it's a mosaic of optimized tiles, each doing what it does best.
Lucas: That's a great way to put it. And the ecosystem is evolving to support that vision. We have open standards like UCIe, design tools that can simulate multi-die thermal and electrical behavior, and foundries offering turnkey packaging services. It's becoming a commodity capability, not a boutique one.
Luna: But there's still a gap: design complexity. The tools for heterogeneous integration are not yet as mature as monolithic design tools. You have to worry about signal integrity across dies, power delivery across the package, and test strategies for partial assemblies.
Lucas: That's a real bottleneck. And it's why companies like Cadence and Synopsys are investing heavily in multi-die simulation and analysis. They need to give designers the ability to verify a system-in-package the way they'd verify a monolithic SoC.
Luna: And testing — you brought up test. With chiplets, you can test each die before assembly, which improves yield. But you also need to test the assembled package, and you can't easily probe internal nodes.
Lucas: Right. So there's a whole new discipline of 'chiplet test' emerging, with built-in self-test circuits and boundary scan standards. It's fascinating but it adds cost.
Luna: Let me ask a pointed question: is heterogeneous integration just a stopgap until we figure out how to make 1-nanometer transistors work economically?
Lucas: I don't think so. Even if we get to 0.5 nanometer, there are fundamental physical limits. The interconnect delay doesn't scale the same way transistors do. So packaging will continue to be a performance differentiator. Plus, the diversity of applications — automotive, industrial, medical — demands specialized blocks that can't all be on the bleeding edge.
Luna: So heterogeneous integration is not a Plan B; it's Plan A for the foreseeable future.
Lucas: Exactly. And the numbers back it up. The market for advanced packaging was about $44 billion in 2025, growing at a compound annual growth rate of around 9 percent. Heterogeneous integration is the fastest-growing segment within that.
Luna: And we're seeing national governments invest too. The US CHIPS Act includes billions for packaging R&D, because it's seen as a strategic capability.
Lucas: Yeah, the National Advanced Packaging Manufacturing Program is a specific initiative. The goal is to make the U.S. a leader in packaging, not just front-end fabrication. Because right now, most advanced packaging happens in Taiwan and Korea.
Luna: So the race isn't just about who can make the smallest transistor; it's about who can integrate the most diverse chips into the smartest package.
Lucas: And that race is wide open. It's a genuinely exciting time in hardware engineering.

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