# Why Chip Designers Are Turning to Carbon Nanotube Interconnects

An episode of [The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations](https://invisiblenetwork.ai/podcast/1896799982), 12 Jun 2026, 13 min.

Audio: https://audio.fexingo.com/business/the-hardware-podcast/episode-0047.mp3

Episode 47 of The Hardware Podcast digs into the quiet shift happening inside chip fabrication lines: carbon nanotube interconnects. Lucas and Luna discuss why copper interconnects are hitting fundamental limits at the 2-nanometer node, how carbon nanotubes can carry more current with less resistance, and what TSMC and IBM have disclosed about their early research. They walk through a specific 2025 paper from the IEEE International Electron Devices Meeting that showed a nanotube-based test structure delivering 30 percent lower latency than copper at equivalent line widths. The episode also covers the manufacturing hurdles — alignment, density, contact resistance — and why this isn't a near-term replacement but a plausible mid-decade transition. Concrete, engineering-focused, and grounded in real data. #CarbonNanotubeInterconnects #ChipDesign #SemiconductorEngineering #TSMC #IBM #CopperLimits #2nmNode #IEDM #InterconnectScaling #Nanoelectronics #HardwarePodcast #Technology #ChipManufacturing #FexingoBusiness #BusinessPodcast #MaterialsScience #AdvancedPackaging #ResistanceCapacitance Keep every episode free: buymeacoffee.com/fexingo

## Transcript

Lucas: So there's this quiet shift happening inside chip fabrication lines that most people outside the industry haven't heard about. It's not about transistor architecture — it's about the tiny wires that connect those transistors.
Luna: The interconnects. We've talked about them before, but I think the last time was episode 31, when we hit the wall with copper.
Lucas: Right. And that wall is getting closer with every new process node. At the 2-nanometer node and below, copper interconnects start to fail — they can't carry enough current without excessive heating, and the resistance-capacitance delay actually becomes the bottleneck, not the transistor speed.
Luna: So what's the alternative? I've heard about cobalt, ruthenium, even graphene.
Lucas: All of those are being investigated. But the one that's generating serious research momentum right now is carbon nanotubes. I'm talking about individual cylindrical molecules of carbon, about one nanometer in diameter, that can carry current densities over a thousand times higher than copper.
Luna: That's an absurd number. But why haven't we seen them in production yet?
Lucas: Because manufacturing them at scale is brutally hard. You need to grow billions of aligned nanotubes perfectly perpendicular to the wafer surface, with consistent chirality — that's the twist pattern that determines whether they conduct like a metal or a semiconductor. And you need to make low-resistance contacts at both ends.
Luna: So we're talking about a material that's theoretically perfect but practically a nightmare.
Lucas: Exactly. But there was a paper at the 2025 IEEE International Electron Devices Meeting — IEDM — that showed a real breakthrough. Researchers from a consortium including TSMC and Stanford demonstrated a test structure using carbon nanotube vias at a 30-nanometer pitch. They measured 30 percent lower latency compared to copper at the same dimensions.
Luna: Thirty percent lower latency. That's not incremental. At those scales, that's transformative for chip performance.
Lucas: It is. And the key was they solved the alignment problem using a new growth technique called 'directional chemical vapor deposition with a plasma bias.' Essentially, they used an electric field during the deposition to force the nanotubes to grow vertically.
Luna: I want to get into the details of that. But first, can we step back and explain why copper is failing in the first place? I think some listeners might not know the physics.
Lucas: Sure. So as feature sizes shrink, the cross-section of a copper wire gets smaller. At some point, the wire becomes narrower than the mean free path of an electron in copper — about 40 nanometers. When that happens, electrons start scattering off the grain boundaries and sidewalls, and resistance skyrockets.
Luna: And that's not just a performance hit. It's also a reliability issue — electromigration.
Lucas: Exactly. The high current density pushes metal atoms along the wire, creating voids and eventually open circuits. For copper, the electromigration limit at sub-10-nanometer line widths is around 10 million amps per square centimeter. Carbon nanotubes can handle more than 10 billion amps per square centimeter without budging.
Luna: So nanotubes don't suffer from electromigration because the carbon-carbon bond is incredibly strong.
Lucas: Right. It's a covalent bond — much stronger than the metallic bond in copper. That's the fundamental advantage.
Luna: But getting that advantage in a real fab is the challenge. What does the manufacturing process actually look like? I've read that they grow nanotubes at temperatures around 600 degrees Celsius. That's too hot for back end of line processing.
Lucas: That's the second big hurdle. The IEDM paper used a lower-temperature process at 400 degrees Celsius by using a cobalt catalyst instead of iron. That's compatible with the thermal budget after the transistors are built. They also demonstrated something called 'density multiplication' — growing nanotubes in a patterned template so that the density is high enough for practical via resistance.
Luna: What density are we talking about?
Lucas: They achieved about 10 to the 12 nanotubes per square centimeter. That's about one nanotube per every 10 nanometers. For a 30-nanometer via, that's roughly 10 nanotubes carrying current in parallel. The contact resistance at the top and bottom was still higher than copper — about 100 ohms per nanotube — but they think they can bring that down with better metallization.
Luna: So it's not ready for prime time, but it's a real proof of concept.
Lucas: Exactly. And there's another angle: IBM has been working on this for over a decade. In 2024, they published a paper showing a carbon nanotube transistor with a 1.8-nanometer gate length. That's smaller than anything silicon can do. But that's a different conversation.
Luna: Let's stay on interconnects. Are there any other materials that could beat nanotubes to market?
Lucas: Ruthenium is probably the nearest-term candidate. It has better electromigration resistance than copper and can be deposited by atomic layer deposition, which gives better conformality in narrow trenches. But its resistivity is higher than copper for large lines. For intermediate and global interconnects, some foundries are already looking at cobalt and molybdenum.
Luna: So nanotubes are more of a long-term play for the most critical vias at the smallest dimensions.
Lucas: That's the consensus. The International Roadmap for Devices and Systems lists carbon nanotubes as a potential interconnect material for the 1-nanometer node and beyond, which would be late 2020s or early 2030s.
Luna: That's still a few years out. But the progress in the last two years has been impressive. I remember seeing a 2023 paper from a team at MIT that showed a nanotube-based interconnect with lower resistance than copper at a 5-nanometer line width.
Lucas: Yeah, that was a big deal at the time. They used a 'doping' technique — exposing the nanotubes to a chemical that increased the carrier concentration. It brought the resistance down by about 40 percent compared to undoped nanotubes.
Luna: So there are multiple levers: alignment, density, doping, contact metal. It's a multi-variable optimization problem.
Lucas: Exactly. And the foundries are starting to invest real money in it. TSMC has a dedicated research group for carbon nanomaterials. Samsung has published papers on nanotube interconnects for DRAM. And the European Union's Horizon Europe program funded a project called nano ict that specifically targets nanotube integration.
Luna: It's not just hype then. There's actual R&D spend behind it.
Lucas: Absolutely. And here's the thing — even if nanotubes only replace the most critical vias in the most advanced chips, that could be a multi billion dollar market. Because those are the chips that go into AI accelerators, high-performance computing, and data centers where every percent of performance matters.
Luna: Speaking of performance, I want to ask about the thermal aspect. Carbon nanotubes have extremely high thermal conductivity — around 3000 watts per meter-kelvin. That's higher than diamond. How does that play into the interconnect story?
Lucas: It's a huge advantage. As chips pack more transistors, heat dissipation becomes a critical bottleneck. Copper interconnects actually contribute to heating because of resistive losses. Nanotubes not only carry current with less loss, but they also conduct heat away from the active regions. So you get a double benefit: lower temperature and lower resistance.
Luna: That's the kind of synergy that could justify the manufacturing complexity.
Lucas: Right. But the integration challenge isn't just about growing nanotubes. You also have to connect them to the rest of the interconnect stack. That means creating a reliable contact between the nanotube via and the copper or ruthenium line above and below. That interface is where a lot of resistance can creep in.
Luna: Have there been any clever solutions for that?
Lucas: One approach is to use a 'cap' layer — a thin metal like palladium that makes a good ohmic contact to nanotubes. Palladium has a work function that matches the nanotube's Fermi level. But palladium is expensive and not commonly used in fabs. Another approach is to use a carbon-based contact, like a graphene layer, but that adds its own complexity.
Luna: So there's still a lot of materials science to be done.
Lucas: Absolutely. But the IEDM paper was a milestone because they showed a functional via chain with thousands of nanotube vias, and the yield was over 90 percent. That's a huge leap from just a few years ago when yield was in the single digits.
Luna: Ninety percent yield in a research setting is promising. In production you need 99.999 percent, but it shows the direction.
Lucas: Exactly. And that kind of progress doesn't happen without sustained funding. Speaking of which — a quick honest thing. This podcast is ad-free, and it stays that way because a small group of listeners chips in monthly through buy me a coffee dot com slash fexingo. It's not a big campaign, it's just what keeps the lights on for shows like this.
Luna: Yeah, it's how we avoid any sponsor pressure and keep digging into topics like carbon nanotube interconnects because they're genuinely interesting — not because someone paid us to talk about them.
Lucas: So if today's technical deep dive gave you something useful, and you want to see more like it, that's the link. And now back to the lab — let's talk about what a carbon nanotube interconnect actually looks like under an electron microscope.
Luna: I've seen those images. They look like a forest of tiny spaghetti, all standing upright.
Lucas: That's exactly the term researchers use — 'nanotube forest.' And the key is to make that forest dense enough and aligned enough that every via has multiple conductive paths. In the IEDM paper, they used scanning electron microscopy to show that the nanotubes were within about 10 degrees of vertical.
Luna: Ten degrees might not sound perfect, but for a via that's only 30 nanometers tall, that's acceptable.
Lucas: Exactly. The aspect ratio is low. And they also used something called 'in-situ Raman spectroscopy' to measure the quality of the nanotubes — checking for defects and the metallic to semiconducting ratio. They found that about 70 percent of the nanotubes were metallic, which is good for interconnects.
Luna: So the characterization tools are also improving alongside the growth techniques.
Lucas: Absolutely. And that's the theme across the whole field — incremental improvements in every step: growth, alignment, contact, characterization. It's not a single breakthrough; it's a thousand small ones.
Luna: Do you think we'll see carbon nanotube interconnects in a commercial chip within the next five years?
Lucas: I think it's more likely in the 2028 to 2030 timeframe, and probably first in a specialized product — maybe a high-bandwidth memory stack or an AI accelerator where the performance gain justifies the cost. By 2032 or so, if the manufacturing matures, it could spread to mainstream logic.
Luna: That's a longer horizon than some people expect. But given the complexity, it's realistic.
Lucas: Yeah. And the nice thing is that the basic physics is solid. It's not a question of 'if' carbon nanotubes can outperform copper — they already do in the lab. It's a question of 'when' we can make them reliably and cheaply enough for a fab.
Luna: I think that 'when' is getting closer with every IEDM paper.
Lucas: Agreed. And for anyone who wants to follow the research, I'd recommend keeping an eye on the IEEE Electron Device Letters and the annual VLSI Technology Symposium. That's where the next big interconnect paper will likely appear.

Shows are listed from Apple Podcasts' charts and directory, and Podcast Index where it is used. Every show and episode belongs to its publisher and plays from the publisher's own feed; this site hosts none of them.