# How Chips Are Printing Their Own Interconnects

An episode of [The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations](https://invisiblenetwork.ai/podcast/1896799982), 24 Jun 2026, 6:53.

Audio: https://audio.fexingo.com/business/the-hardware-podcast/episode-0071.mp3

In this episode of The Hardware Podcast with Fexingo, Lucas and Luna explore how chipmakers are turning to additive manufacturing — essentially 3D printing — to build the microscopic copper interconnects that connect transistors on a die. We focus on a specific breakthrough from a company called Applied Nanotools, which demonstrated a process called 'superconformal electrodeposition' that deposits copper in trenches just 10 nanometers wide without voids. Lucas explains why traditional subtractive etching hits a wall below 7 nanometers, and how printed interconnects could reduce resistance by 40 percent compared to conventional damascene processes. Luna asks whether this technique is production-ready or still a lab curiosity, and Lucas points to early adoption by a major memory manufacturer in 2025. We also touch on the implications for chip yield, power density, and the roadmap beyond 2-nanometer nodes. If this episode gives you a concrete insight you can share, listener support at buy me a coffee dot com slash fexingo keeps the show ad-free. #AdditiveManufacturing #ChipInterconnects #AppliedNanotools #SuperconformalElectrodeposition #CopperPrinting #NanometerFabrication #SemiconductorManufacturing #3DPrintedChips #DamasceneProcess #ResistanceReduction #NodeScaling #MemoryManufacturing #ChipYield #PowerDensity #Technology #HardwarePodcast #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo

## Transcript

Lucas: You know how, for decades, we built chips by carving away material — subtractive manufacturing — like a sculptor chipping marble? Well, a growing number of chipmakers are flipping that entirely. They're now printing the interconnects — adding copper exactly where it's needed, atom by atom.
Luna: So, additive manufacturing for the microscopic wiring on a die? I've heard whispers about this at the recent SPIE conferences, but is it production-ready yet?
Lucas: That's the big question. Let's focus on one specific technique that's getting real traction: superconformal electrodeposition. A company called Applied Nanotools demonstrated this for 10-nanometer-wide trenches — that's about a hundred atoms wide — and they filled them without any voids. Traditional damascene, which is the current standard, starts to leave gaps below about 7 nanometers because the copper doesn't plate evenly.
Luna: And voids kill reliability — they create hotspots and current crowding, right?
Lucas: Exactly. So Applied Nanotools' process uses a special electrolyte with additives that accelerate deposition at the bottom of the trench. It's like the copper grows from the bottom up, rather than pinching off at the top. They reported a 40 percent reduction in line resistance compared to equivalent damascene lines. For a high-performance compute chip, that's huge — less heat, faster signaling.
Luna: If today's conversation gave you something useful — maybe a clearer picture of how chips are built — the way we keep these episodes ad-free is listener support. A small contribution at buy me a coffee dot com slash fexingo helps us keep digging into the engineering details.
Lucas: And we genuinely mean that — no sponsors, no interruptions, just the tech conversation. So back to those copper lines: the key challenge is scaling this to high-volume manufacturing. Applied Nanotools is working with a major memory manufacturer — I can't name them, but they're one of the top three DRAM producers — and they've already integrated this into a test vehicle for a 2025 product.
Luna: Memory makes sense — DRAM is all about dense, narrow lines with tight pitch. But what about logic chips? Will we see this in CPUs or GPUs anytime soon?
Lucas: Probably not for the next couple of nodes. Logic has more complex routing and requires multiple layers of interconnects with different widths. But the industry roadmap — the IEEE International Roadmap for Devices and Systems — actually flags additive interconnect as a critical technology for sub-2-nanometer nodes. The reason is that at those dimensions, subtractive etching just can't maintain the aspect ratios needed.
Luna: So it's a bridge to something like atomic layer deposition of metals? Or a standalone solution?
Lucas: It could be both. For the tightest pitches — think 12-nanometer pitch or below — superconformal electrodeposition might be the only practical way. For wider lines, traditional methods still work fine. So it's likely a hybrid approach: print the critical layers, etch the rest.
Luna: What about the equipment side? Does this require entirely new fab tools, or can they retrofit existing electroplating chambers?
Lucas: Retrofitting is possible, but the electrolyte chemistry is different, and the process control is much tighter. Applied Nanotools uses a pulsed current waveform — very precisely timed — to control the deposition. That means new power supplies and control software. But the chamber itself is similar to what's used for copper damascene today. So the capital expenditure isn't as high as, say, moving from DUV to EUV lithography.
Luna: That makes it more palatable for the fabs. And the yield impact? I imagine fewer voids means better electrical performance.
Lucas: Exactly. One of the big yield killers in advanced nodes is 'via resistance variation' — essentially, the connection between metal layers isn't consistent because of tiny voids. Additive interconnects can reduce that variation significantly. Applied Nanotools showed a 30 percent reduction in resistance spread across a wafer. That translates directly to higher binning yields for high-performance parts.
Luna: So this is one of those 'silent' improvements — no one outside the fab will ever see it, but it makes every chip a little faster and cooler.
Lucas: Right. And it's not just about speed. Lower resistance means you can shrink the wire width without increasing RC delay. That's how you keep scaling density while maintaining performance. Without something like this, the industry hits a wall at around 3-nanometer equivalent.
Luna: Is there any competing approach? I've read about using graphene or carbon nanotubes for interconnects.
Lucas: Those are long-term bets — maybe for the 1-nanometer era. But they have their own problems: contact resistance, integration with copper, and manufacturing complexity. Superconformal electrodeposition is much closer to production because it's still copper, just deposited differently. It leverages the existing supply chain for copper precursors and barrier materials.
Luna: So it's a pragmatic improvement, not a moonshot. I like that. When do you think we'll see the first commercial chip using this technique?
Lucas: If the memory manufacturer I mentioned ships in 2025 as planned, then that product will be the first. For logic, I'd guess 2027 or 2028 — roughly the 2-nanometer node for leading-edge foundries. Intel has published research on additive interconnects for their 18A node, but they haven't committed to it in their roadmap yet.
Luna: So we're maybe two generations away from mainstream adoption. But the engineering community seems excited.
Lucas: The latest IEDM conference had three papers on additive interconnect techniques — that's triple from five years ago. The materials science is maturing fast. And what's interesting is that it also opens the door to 3D stacking of interconnects — printing vertical vias with perfect aspect ratios. That could change how we design chiplet interfaces.
Luna: That's a whole other episode — printing the connections between chiplets. But for today, I think we've painted a clear picture of how printing copper lines could keep Moore's Law alive for another node or two.
Lucas: And without the drama of new transistor architectures. Sometimes the most impactful changes are in the wiring, not the switches themselves.

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