# How Chips Are Using On-Chip Antennas for Wireless Interconnects

An episode of [The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations](https://invisiblenetwork.ai/podcast/1896799982), 8 Jul 2026, 11 min.

Audio: https://audio.fexingo.com/business/the-hardware-podcast/episode-0098.mp3

Episode 98 of The Hardware Podcast explores the latest in on-chip antennas for wireless interconnects—a technology that replaces traditional wired buses with millimeter-wave radio links inside a package. Lucas and Luna discuss how companies like Intel and Samsung are integrating tiny antennas onto silicon to reduce latency and power in multi-chip systems, with specific data on the 60 GHz band achieving 20 Gbps per link. They break down the engineering trade-offs: antenna efficiency versus chip area, and the challenge of interference in dense arrays. The episode also touches on a startup applying this to AI accelerators for modular scaling. A concrete example from a recent ISSCC paper shows a 4×4 antenna array delivering 50% lower power than wired SerDes. #OnChipAntennas #WirelessInterconnects #MillimeterWave #ChipDesign #Semiconductors #Intel #Samsung #ISSCC #AIAccelerators #MultiChipModules #60GHz #AntennaArray #SerDes #LowPower #HardwareEngineering #Technology #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo

## Transcript

Lucas: So you've got a high-performance AI accelerator — maybe a dozen chiplets on a single interposer, and the data moving between them is still running through physical traces. That's getting slower and more power-hungry as the bandwidth requirements climb.
Luna: Right, and at some point the wires become the bottleneck. So what's the fix? Replace the wires with — what, antennas?
Lucas: Exactly. On-chip antennas for wireless interconnects. Instead of routing a high-speed signal through copper from one die to another, you transmit it over a millimeter-wave radio link — inside the package. We're talking about antennas that are literally fabricated on the silicon die itself, using the metal stack layers.
Luna: I remember seeing prototypes from Intel a few years ago at ISSCC. They were showing 60 GHz links with data rates around 20 gigabits per second per channel.
Lucas: That's the right reference. Intel's work around 2017–2018 was really foundational. They demonstrated a 60 GHz transmitter and receiver integrated into a CMOS chip, with on-die dipole antennas. The link budget was tight — you're transmitting maybe a few milliwatts of power over a distance of a few centimeters — but the efficiency was compelling. They got about 2 picojoules per bit, which is significantly better than a typical high-speed SerDes at comparable data rates.
Luna: And the latency? Because for AI training loops, that's almost as important as power.
Lucas: Sub-nanosecond. That's the killer feature. With a wired SerDes, you have clock recovery, equalization, forward error correction — all of that adds tens of nanoseconds per hop. With a wireless link, once the antenna and the transceiver are on the same die, the propagation delay is essentially just the time of flight through air, which is negligible. So you get deterministic, ultra-low latency.
Luna: But I've always wondered — how do you fit an efficient antenna on a chip that's only a few millimeters on a side? At 60 GHz, the wavelength is about 5 millimeters in free space, so a half-wave dipole would be 2.5 millimeters — that's huge for a die.
Lucas: That's exactly the engineering trade-off. You can't do a full-size dipole. So researchers use techniques like meandering the antenna, or using slot antennas, or leveraging the package substrate. Some designs use a patch antenna on the top metal layer with a ground plane below — but the efficiency drops. A typical on-chip antenna might have 10 to 30 percent radiation efficiency, compared to 90 percent for an off-chip antenna. The trick is that the link is so short — just a few centimeters — that even a low-efficiency antenna is enough if the receiver is sensitive enough.
Luna: So the path loss is small enough to compensate for the poor antenna gain. That makes sense.
Lucas: Right. And now companies like Samsung are taking this into production for certain multi-chip modules. They've published work on a 28 GHz wireless interconnect for memory and logic chiplets. The idea is to eliminate the expensive interposer and just use a standard organic package with antennas embedded in the redistribution layer.
Luna: That would be a huge cost saving. Interposers with through-silicon vias are expensive, and they limit the die size.
Lucas: Exactly. So wireless interconnects let you scale to many more chiplets without the interposer complexity. A startup called Mixel has been working on a standard for 'wireless die to die' links, and there's an IEEE 802.15 task group looking at millimeter-wave communication for package-level interconnects.
Luna: I want to drill into one specific case. There was a paper at ISSCC 2025 — I think from a team at Berkeley — that showed a 4x4 antenna array on a 28 nanometer CMOS chip, beamforming to steer the signal to specific chiplets.
Lucas: Yes, that was a big step. They used phased-array beamforming at 60 GHz with 16 elements, each with its own phase shifter. They achieved a spatial resolution of about 10 degrees, so you can address different chiplets in the package by steering the beam. The aggregate data rate was 80 gigabits per second across four simultaneous links, and the power per bit was down to 1.5 picojoules.
Luna: That's impressive. And the chip area overhead? Sixteen antennas plus phase shifters must take up a lot of die area.
Lucas: It does. The antenna array alone was about two square millimeters — which is nontrivial on a 28 nanometer chip. But for a large AI accelerator die that's already 400 square millimeters, that's half a percent. The trade-off is that you save area on the interposer and on the SerDes channels. So net area can be a win.
Luna: And the interference? With multiple chips transmitting in the same package, you'd worry about crosstalk.
Lucas: That's where the beamforming helps. You can spatially separate the links. Plus, you can use different frequency channels — there's 9 GHz of unlicensed spectrum around 60 GHz — so you can do frequency-division as well. The Berkeley group showed a signal to interference ratio of better than 20 decibels with two simultaneous beams.
Luna: One thing I find fascinating is how this intersects with the broader push toward chiplets and disaggregated SoCs. If you can wirelessly interconnect chiplets, you're no longer tied to a single silicon process. You could have a 3 nanometer AI core, a 7 nanometer memory controller, and a 28 nanometer analog chip all in the same package, talking over wireless links.
Lucas: That's the vision. And it's already happening in some research prototypes. I've seen a design where a 5 nanometer logic die communicates with a 12 nanometer SRAM die using a 60 GHz link. The latency was under 2 nanoseconds end to end, and the energy per bit was 30 percent lower than a comparable wired SerDes.
Luna: What about reliability? Wireless links in a package have to deal with temperature variations, power supply noise, and potential blocking by other components.
Lucas: That's an active area of research. Some groups use adaptive equalization and automatic gain control to handle varying channel conditions. Others use multiple-input multiple-output techniques for diversity. The package environment is actually quite benign compared to an outdoor wireless link — the channel is static, the distances are fixed, and you can characterize it at design time. So you can tune the link for maximum efficiency.
Luna: Are there any commercial products using this yet? Or is it still lab-only?
Lucas: It's mostly in the research and prototyping phase for high-volume products. But some niche applications have adopted it. For example, in some high-end networking equipment, where you need low latency between switch chips, I've heard of companies using 60 GHz interconnects inside the chassis. And in the defense sector, there are systems using wireless interconnects for radar processing modules.
Luna: And if today's tech conversation gave you something usable — maybe a new way to think about chip design or a specific efficiency figure — that's exactly the kind of content we try to keep free and accessible here. We don't run ads, so listener support is what keeps the show going. If you find value in episodes like this, you can support us at buy me a coffee dot com slash fexingo.
Lucas: Yeah, and we really appreciate that. It lets us stay independent and dive deep into topics without worrying about sponsors. So back to the technology — one of the biggest challenges I think is standardization. Right now, every research group uses their own frequency, modulation, and protocol. For wireless interconnects to become mainstream, the industry needs a common interface, like what the MIPI Alliance did for wired links.
Luna: Is there any movement on that? I know the IEEE 802.15.3e task group was working on a standard for chip to chip millimeter wave communication.
Lucas: They are, but it's slow. The draft standard is expected around 2027. It defines a physical layer at 60 GHz with multiple data rates up to 100 gigabits per second, and a media access control layer that supports point to point and star topologies. If that gets ratified, we'll probably see commercial IP blocks from companies like Mixel or Samsung within a year or two.
Luna: That would be a game changer for AI hardware. Imagine a modular AI accelerator where you can add compute chiplets by just placing them on a substrate — no rewiring, just a wireless handshake.
Lucas: Exactly. And that's what some startups are already prototyping. There's a company called ASOCS that's working on a 'wireless fabric' for AI data centers. They're using on-chip antennas at 28 GHz to connect accelerator dies on a PCIe card. They claim a 40 percent reduction in latency compared to PCIe Gen 5.
Luna: So the tangible benefit is real. I'm curious about the near-term adoption timeline. When do you think we'll see wireless interconnects in a mainstream consumer chip, like a laptop processor?
Lucas: I'd say five to seven years. The biggest hurdle is the cost of integrating antennas and transceivers on a logic die. For a mobile processor, the area penalty might be too high. But for server CPUs and GPUs, where the die size is large and the bandwidth demands are extreme, we could see hybrid packages with wireless interconnects for certain critical paths by 2030.
Luna: And what about the thermal impact? You've got power amplifiers generating heat right next to the compute cores.
Lucas: That's a concern. The power amplifiers for 60 GHz can have efficiencies around 20 to 30 percent, so they dissipate heat. But the total power per link is low — maybe 50 milliwatts per gigabit per second — so the thermal density is manageable if you spread the links out. Some designs put the wireless transceivers on a separate die or on the package substrate itself, which helps with thermal isolation.
Luna: So there are multiple paths to making this work. I think the key takeaway is that on-chip antennas are no longer just a curiosity. They're becoming a practical tool for breaking the wiring bottleneck.
Lucas: Absolutely. And the progress in the last five years — from Intel's early demos to the Berkeley phased array to Samsung's production-ready prototypes — suggests that we're past the inflection point. The question now is not if, but when and where wireless interconnects will first appear in volume.
Luna: And for listeners who want to keep up, we'll keep tracking the ISSCC proceedings and the IEEE standards work. Thanks for tuning in to The Hardware Podcast.
Lucas: Until next time.

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