# How Chips Use On-Chip Rad-Hard Design for Space Electronics

An episode of [The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations](https://invisiblenetwork.ai/podcast/1896799982), 21 Jul 2026, 9:29.

Audio: https://audio.fexingo.com/business/the-hardware-podcast/episode-0125.mp3

In this episode of The Hardware Podcast, Lucas and Luna explore on-chip radiation-hardened design for space electronics. They focus on how the European Space Agency's latest microcontroller, the LEON5, uses triple modular redundancy and silicon-on-insulator technology to survive the harsh radiation environment of low-Earth orbit and deep space. They break down the specific failure mechanisms—single-event upsets and latch-ups—and how rad-hard chips differ from traditional terrestrial processors. The conversation also touches on the cost implications and whether rad-hard trickles down to critical infrastructure on Earth. If you've ever wondered how microchips survive in space, this episode delivers a concrete look at the engineering trade-offs. #SpaceElectronics #RadHard #LEON5 #ESA #TripleModularRedundancy #SiliconOnInsulator #SingleEventUpset #LatchUp #Microcontrollers #AerospaceEngineering #RadiationHardening #Technology #HardwarePodcast #FexingoBusiness #BusinessPodcast #ChipDesign #Semiconductors #SpaceTech Keep every episode free: buymeacoffee.com/fexingo

## Transcript

Lucas: So you've got a satellite in low-Earth orbit, zipping along at about 17,500 miles per hour, and every second it's getting bombarded by high-energy protons and heavy ions. For a standard commercial chip, that's a death sentence.
Luna: Right — bit flips, latch-ups, total destruction. I've read that in LEO, you can get a single-event upset every few days on a regular processor.
Lucas: Exactly. And that's why space-grade chips are designed specifically for radiation-hardness — what the industry calls 'rad-hard.' Today I want to focus on a specific case: the European Space Agency's LEON5 microcontroller, which is a rad-hard sparc based chip that's been flying on ESA missions for years.
Luna: LEON5 — that's the latest iteration, right? I think it's used on the ExoMars rover and some of the Copernicus Earth observation satellites.
Lucas: That's right. The LEON family goes back to the early 2000s. The LEON5 is built on a 28-nanometer process — pretty old by terrestrial standards, but that's intentional. Older nodes with larger transistor geometries are naturally more resistant to radiation because there's more physical charge to flip a bit.
Luna: So newer isn't better in space. That's a fascinating trade-off — you're choosing reliability over raw speed.
Lucas: Exactly. But it's not just the process node. The LEON5 uses a set of design techniques that are the real secret sauce. The most fundamental is triple modular redundancy — TMR. Every critical logic gate is triplicated, and a voting circuit decides the majority output. So if one gate gets hit by a proton and flips, the other two still agree, and the system carries on.
Luna: And that's on top of error-correcting code memory — EDAC — which corrects single-bit flips in SRAM and registers.
Lucas: Exactly. The LEON5 uses EDAC with single-error correction, double-error detection on all its internal caches and main memory. Combine that with TMR on the control logic, and you get a chip that can tolerate multiple radiation strikes per day without ever crashing.
Luna: But TMR comes with a huge area and power penalty — three times the logic, three times the power. How do they manage that in a satellite, where power is already at a premium?
Lucas: Great question. The answer is selective TMR — you don't triplicate everything. The LEON5's designers analyzed the most critical paths — the pipeline control, the memory controller, the register file — and applied TMR only there. Less critical units, like the peripheral interfaces, get dual redundancy with error detection, not full voting.
Luna: So it's a risk-weighted approach. Cost-efficient for space, where every gram of payload costs thousands of dollars to launch.
Lucas: Right. And another key technique is silicon-on-insulator, or SOI, technology. The LEON5 is fabricated on a 28-nanometer fully depleted SOI process. In SOI, a buried oxide layer isolates the transistor from the silicon substrate, which drastically reduces the volume where ionizing radiation can generate charge.
Luna: Meaning fewer single-event upsets in the first place, before the redundancy even kicks in. It's a two-layer defense: SOI reduces the problem, TMR handles what slips through.
Lucas: Exactly. And there's a third layer: the chip design includes guard rings and hardened flip-flops that are less sensitive to charge collection. It's not just one trick — it's a whole stack of hardening techniques.
Luna: What about latch-up? That's the other big killer in space — when an ion triggers a parasitic thyristor that shorts power to ground.
Lucas: Right. Latch-up can destroy a chip in milliseconds. The LEON5 uses a combination of guard rings and well-tied contacts to reduce the gain of those parasitic structures, plus current-limiting circuits that detect a latch-up condition and power-cycle the affected block before it fries.
Luna: So the chip can actually reboot a portion of itself mid-flight.
Lucas: Exactly. The LEON5 has a built-in watchdog timer and a low-level supervisor that can reset just the CPU core if it detects an anomaly, without losing the satellite's state entirely.
Luna: And this is all on a 28-nanometer node. I know the US military uses rad-hard chips on older 150-nanometer processes — are we seeing a shift toward smaller nodes for space?
Lucas: Yeah, there's a definite trend. NASA's upcoming High-Performance Spaceflight Computing processor is on a 12-nanometer FinFET process. FinFETs have a natural advantage because the fin geometry inherently reduces charge collection volume. But the trade-off is increased sensitivity to total ionizing dose — the cumulative radiation over years — which degrades transistor threshold voltage.
Luna: So smaller nodes require more sophisticated mitigation for total dose effects. That usually means thicker oxide layers or special layout techniques.
Lucas: Right. And this is where we get into total-dose hardening — techniques like enclosed layout transistors and annular gate structures that prevent leakage paths from building up over time.
Luna: I also wonder — do any of these rad-hard techniques ever trickle down to terrestrial applications? Like for medical implants or autonomous driving, where reliability is critical?
Lucas: They do, actually. The automotive industry is starting to adopt some of these techniques for safety-critical chips — especially TMR for brake-by-wire and steer-by-wire systems. And high-reliability memory chips for financial servers use EDAC codes originally developed for space. But the cost is still prohibitive for mass-market consumer electronics.
Luna: So rad-hard is still a niche, but it's a foundational one. Without these chips, we wouldn't have GPS, weather satellites, or deep-space science.
Lucas: Exactly. And that's the thing that fascinates me — it's a hidden layer of engineering that makes the modern world possible, but most people have no idea it exists.
Luna: Speaking of things that make the show possible — and I say this genuinely — if you're getting value out of these deep dives into chip design, it's listener support that keeps the podcast ad-free and independent.
Lucas: Yeah, it's a small thing but it matters. A couple of dollars a month — buy me a coffee dot com slash fexingo — goes directly toward research and production. No big corporate sponsor, no ads.
Luna: We really appreciate it. And if you just listen and enjoy, that's great too. But if this episode gave you something new, consider throwing a few bucks in the hat.
Lucas: Alright — back to the LEON5. One more area I want to hit: how they test these chips. You can't just launch and hope for the best.
Luna: Right — they use particle accelerators to simulate radiation environments. I know ESA uses the Cyclotron Resource Centre in Belgium for heavy-ion testing.
Lucas: Exactly. They bombard the chip with a beam of heavy ions at different energies to measure the cross-section for single-event upsets — basically, the probability that a given particle will cause a failure. Then they model the expected upset rate for the orbit the satellite will fly.
Luna: And if the upset rate exceeds the mission requirements, you go back and redesign.
Lucas: Exactly. It's a whole design for test ecosystem that's built into the chip from the start. The LEON5 includes built-in self-test circuits for fault injection during testing, so they can verify the TMR voting logic works without having to hit every node with a real particle.
Luna: That's elegant — test the robustness by injecting faults digitally, then confirm with real radiation at the end.
Lucas: It's a smart verification strategy. And it's one reason why space chips take years longer to develop than their commercial counterparts.
Luna: So if I'm a chip designer listening, what's the takeaway? What's the one technique that's most accessible for terrestrial reliability?
Lucas: I'd say EDAC memory is the lowest-hanging fruit. Most modern chip designs already have some form of it, but many systems don't enable it. If you're building a mission-critical device, turn on the EDAC. The area cost is maybe 5 to 10 percent, but the reliability gain is enormous.
Luna: Fair point. TMR is overkill for a lot of applications, but error correction is nearly free in terms of design effort.
Lucas: Exactly. And that's the beauty of rad-hard design — it's not a monolith. You can pick the level of hardening that matches your risk tolerance.
Luna: Well, I'm going to be looking at my phone a little differently now, knowing the tech that makes satellites work.
Lucas: Same here. Next time it's cloudy, I'll remind myself that there's a rad-hard LEON5 up there beaming my GPS signal through it.

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