# How Chips Use On-Chip Capacitors to Stabilize Power

An episode of [The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations](https://invisiblenetwork.ai/podcast/1896799982), 3 Jul 2026, 10 min.

Audio: https://audio.fexingo.com/business/the-hardware-podcast/episode-0088.mp3

In this episode of The Hardware Podcast, Lucas and Luna explore how chip designers are embedding tiny capacitors directly into silicon to smooth out power delivery and reduce noise. They discuss the physics of decoupling capacitors, why traditional off-chip solutions are hitting limits at advanced nodes, and how on-chip deep-trench and metal-insulator-metal capacitors are enabling faster, more efficient processors. The hosts use specific examples from recent industry research and development, including data from a 2025 ISSCC paper on a 3-nanometer test chip that reduced voltage droop by 35 percent. They also touch on the trade-offs in area and leakage current. A natural donation appeal ties the episode's theme of improving chip performance to supporting ad-free tech journalism. #OnChipCapacitors #PowerDelivery #SemiconductorDesign #DecouplingCapacitors #DeepTrenchCapacitor #MIMCapacitor #IRDrop #VoltageDroop #ChipDesign #AdvancedNodes #3Nanometer #ISSCC #PowerIntegrity #HardwareEngineering #Technology #FexingoBusiness #BusinessPodcast #HardwarePodcast Keep every episode free: buymeacoffee.com/fexingo

## Transcript

Lucas: If you look at a modern processor die under a microscope — and I mean a really good one — you will see thousands of tiny little rectangles scattered across the surface, often between the logic blocks and the memory arrays.
Luna: Those are capacitors, right? Not just fill structures?
Lucas: Exactly. They are on-chip decoupling capacitors — and they are absolutely critical for keeping the chip stable. Every time a transistor switches, it draws a pulse of current. If the power delivery network can't respond instantly, the voltage at that transistor droops. If it droops too far, the logic fails. So you need local energy storage right there, on the die, to supply that instantaneous current.
Luna: So the capacitors are basically tiny reservoirs that smooth out the power supply.
Lucas: Precisely. Think of them as surge tanks for electrons. Without them, the voltage on the power grid would bounce all over the place — especially as clock frequencies climb and more transistors switch simultaneously. At frequencies above a gigahertz, the inductance of the package and the board traces makes it impossible for off-chip capacitors to respond fast enough. You need capacitance that is literally within microns of the switching transistors.
Luna: And this becomes more critical as we shrink geometries, right? Because the wires get thinner, resistance increases, and the overall noise margin shrinks.
Lucas: That is exactly the problem. At 7 nanometer and below, the power delivery challenge is one of the top constraints on performance. Designers are using two main types of on-chip capacitors: deep-trench capacitors and metal insulator metal capacitors, or m i m capacitors. Deep trench capacitors are etched into the silicon substrate — you dig a narrow, deep hole, line it with a dielectric, and fill it with conductive polysilicon. That gives you a huge surface area in a small footprint, so you can get tens of nanofarads per square millimeter.
Luna: But aren't deep trenches expensive to manufacture? They add extra process steps.
Lucas: They do. That is why m i m capacitors are more common in the upper metal layers. You deposit a thin layer of high-k dielectric — something like hafnium oxide — between two metal plates. They are easier to integrate with the standard back end of line process, and they offer good density, though typically less than deep trenches. A lot of modern chips use both: deep trenches for bulk decoupling near the power grid, and m i m caps for local, fine-grained decoupling right next to logic cells.
Luna: I read a paper from the 2025 i s s c c — the International Solid-State Circuits Conference — where a team from a major foundry showed a test chip at 3 nanometer that used a combination of deep trench and m i m capacitors. They claimed a 35 percent reduction in voltage droop during high-activity bursts.
Lucas: That is exactly the kind of data that drives the industry. A 35 percent reduction in droop means you can either run the chip at a lower nominal voltage — saving power — or push the clock frequency higher without risking errors. In that same paper, they also showed that the on-chip capacitors occupied about 12 percent of the die area. That is a significant real estate cost, but the trade-off is worth it for high-performance processors.
Luna: Twelve percent is a lot. But I guess if it lets you boost performance by 10 or 15 percent, it pays for itself.
Lucas: Exactly. And there is another angle: the capacitors also help with electromagnetic interference. By providing a low-impedance path at high frequencies, they reduce the amount of noise that couples into the substrate and into neighboring circuits. That is especially important for mixed-signal chips that combine digital logic with sensitive analog or radio-frequency blocks.
Luna: So the capacitors are doing double duty — power integrity and signal integrity.
Lucas: Right. There is even research into using ferroelectric materials for on-chip capacitors — materials that have a very high dielectric constant and can store more charge per unit area. But those are still experimental. The mainstream today is high-k dielectrics like hafnium dioxide or zirconium dioxide.
Luna: What about leakage? If the dielectric is too thin, you get current leaking through the capacitor, which wastes power.
Lucas: That is a real concern. As you scale the dielectric thickness to increase capacitance, leakage current grows exponentially. So there is an optimal thickness that balances density and leakage. For m i m caps, the dielectric is typically around 5 to 10 nanometers thick. For deep trenches, the dielectric can be a bit thicker because the geometry gives you more area, but the aspect ratio — the depth to width ratio — is extreme, sometimes over 50 to 1. Etching those trenches uniformly across a whole wafer is a huge manufacturing challenge.
Luna: I imagine that's one reason why not every chip uses deep trench capacitors. Maybe only the high-end server CPUs and GPUs.
Lucas: That is correct. Consumer chips, like smartphone application processors, tend to rely more on m i m capacitors because they are cheaper to integrate. But even there, the amount of on-chip capacitance is staggering. A typical flagship phone SoC might have on the order of 100 nanofarads of on-chip decoupling capacitance, spread across hundreds of thousands of individual capacitor structures. That is a huge number.
Luna: And the design tools have to account for all of that. The place and route software has to decide where to put the capacitors to minimize the impedance at the most critical switching nodes.
Lucas: Yes. It's a complex optimization problem. You have to model the entire power delivery network — the package, the board, the on-chip grid, and the capacitors — as a distributed r l c network. Then you run simulations to find the 'hot spots' where voltage droop is worst, and you add more capacitance there. It's iterative and time-consuming.
Luna: But it's clearly worth it. I mean, without these on-chip capacitors, we wouldn't be able to run chips at the clock speeds we do today.
Lucas: Absolutely. On-chip capacitors are one of those unsung enablers of modern semiconductor performance. They don't get the attention of transistor architecture or lithography, but they are just as essential.
Luna: You know, speaking of things that are essential but don't get enough attention — this podcast is supported entirely by listeners like you. And if today's deep dive into chip power delivery gave you something useful, you can help keep these conversations going by visiting buy me a coffee dot com slash fexingo.
Lucas: Yeah, we don't run ads, so listener contributions are what keep the show ad-free and independent. It's a small way to support the kind of technical detail we try to bring each episode.
Luna: Exactly. And now, back to capacitors. Lucas, you mentioned ferroelectric materials earlier. What is the timeline for those reaching commercial chips?
Lucas: Good question. Ferroelectric capacitors — often based on hafnium zirconium oxide — have been demonstrated in research labs, but they have reliability issues. The polarization switching can degrade over time, and the manufacturing control is not yet mature. I would guess we are at least five years away from seeing them in a mainstream product. But they could offer a step-change in density, maybe three to four times higher capacitance per area than current m i m caps.
Luna: That would be huge. It could free up die area for more logic or reduce the cost of the chip.
Lucas: Exactly. And there is also work on using on-chip capacitors not just for decoupling, but for energy storage in power-management circuits — like charge pumps and voltage regulators. Some designs use the on-chip capacitance as a temporary energy buffer to handle load transients.
Luna: So on-chip capacitors are becoming a multipurpose component. They started as a necessary evil to manage power noise, and now they are being designed in as intentional elements of the power delivery architecture.
Lucas: That is a great way to put it. And as chips continue to scale, the importance of these tiny structures will only grow. The next frontier is integrating capacitors into the interposer or the package itself — what some call '2.5D' or '3D' capacitance. That could offload some of the area burden from the die.
Luna: But that adds complexity to the packaging, which is already getting more complex with chiplets and hybrid bonding.
Lucas: True. But the industry is moving in that direction because the benefits are clear. Every time you reduce the distance between the capacitor and the load, you reduce the inductance and improve the transient response. So embedding capacitors in the silicon interposer — right under the chip — is a logical next step.
Luna: I've seen some papers from i m e c and Fraunhofer on that. They are using deep trench capacitors in glass interposers.
Lucas: Yes. Glass has excellent electrical properties — low loss, good dimensional stability — and you can etch high-aspect-ratio trenches in it. That could be a game-changer for high-bandwidth memory and AI accelerators.
Luna: So on-chip capacitors are not just a passive component anymore. They are becoming a design feature that influences the entire system architecture.
Lucas: Exactly. And it's a reminder that sometimes the smallest structures have the biggest impact on performance.

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