# How Chips Are Using On-Chip Digital Twins for Real-Time Simulation

An episode of [The Hardware Podcast with Fexingo: Chips, Devices, and Electronics Engineering Conversations](https://invisiblenetwork.ai/podcast/1896799982), 11 Jul 2026, 11 min.

Audio: https://audio.fexingo.com/business/the-hardware-podcast/episode-0105.mp3

In episode 105 of The Hardware Podcast, Lucas and Luna dive into the emerging use of on-chip digital twins — miniature virtual replicas of a chip's own circuits running in real time on the same silicon. They explore how companies like Siemens and Ansys are enabling this technology for adaptive power management, predictive failure detection, and dynamic performance tuning. The hosts discuss a specific case: a recent paper from imec demonstrating a 7-nanometer test chip that uses an on-chip digital twin to reduce power consumption by 18% under varying workloads. Lucas explains how the twin models thermal and electrical stress at the transistor level, while Luna questions the overhead cost and design complexity. The conversation covers the difference between traditional simulation and on-chip digital twins, the role of machine learning in creating compact models, and why this could change how chips handle reliability in automotive and data center applications. Tune in for a focused look at a technology that bridges simulation and real-time control. #OnChipDigitalTwins #DigitalTwin #Semiconductor #Imec #Siemens #Ansys #PowerManagement #PredictiveFailure #AdaptiveComputing #RealTimeSimulation #ThermalModeling #Reliability #AutomotiveChips #DataCenter #MachineLearning #Technology #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo

## Transcript

Lucas: Luna, I want to talk about something that sounds almost recursive — chips that simulate themselves while they're running. On-chip digital twins.
Luna: Okay, I need that explained. A digital twin is normally a virtual model of a physical system, like a jet engine or a factory. You're saying we put that inside the chip itself?
Lucas: Exactly. Instead of simulating a chip on a separate server during design, you embed a lightweight, real-time model of the chip's own circuits onto the same piece of silicon. That twin runs alongside the actual hardware, mirroring its electrical and thermal state.
Luna: But why would you need that? If the chip is already there, can't you just measure the actual voltage and temperature with sensors?
Lucas: You can, but sensors are discrete and sparse. They give you maybe a few dozen data points. A digital twin gives you a continuous, high-resolution map of what every transistor is doing — or at least a statistically accurate approximation. And it can predict what's about to happen, not just report what's happening.
Luna: So it's like having a crystal ball for your chip. What's the use case that's driving this right now?
Lucas: Power management, for one. A recent paper from imec — that's the Belgian nanoelectronics research institute — demonstrated a 7-nanometer test chip with an on-chip digital twin that reduced power consumption by 18 percent under dynamic workloads. The twin models thermal and electrical stress at the transistor level and adjusts voltage and frequency in microseconds.
Luna: Eighteen percent is huge for a data center chip where power is the biggest cost. But is the overhead worth it? The twin itself consumes area and power.
Lucas: That's the trade-off. The imec chip used about 5 percent of the die area for the twin logic and memory. The power overhead was around 3 percent. So net savings are still around 15 percent after accounting for the twin's own consumption. And that's without even optimizing the twin architecture.
Luna: I can see this being really attractive for automotive chips too. If you can predict a failure mode before it happens, you can throttle down or switch to a redundant path.
Lucas: Exactly. Reliability is a huge driver. For autonomous driving systems, a chip that can simulate its own aging — electromigration, oxide breakdown — and adjust its operation in real time could extend safe operating life by years. There's work from Siemens and Ansys on creating what they call 'runtime digital twin builders' that generate compact models automatically from the chip's design database.
Luna: How compact are we talking? The full simulation model of a modern chip could be gigabytes. You can't fit that on-chip.
Lucas: No, you can't. The trick is model-order reduction. You take the full physical model — say, a thermal finite-element mesh with millions of nodes — and reduce it to a system of maybe a few hundred differential equations that capture the dominant dynamics. Machine learning is being used to find those reduced models automatically. Ansys has a tool called Twin Builder that does exactly that, and it can generate a model small enough to fit in a few kilobytes of on-chip memory.
Luna: So the on-chip twin isn't a perfect replica. It's a smart approximation that's good enough for the decisions you need to make.
Lucas: Right. And it gets updated periodically from real sensor readings to correct drift. That's the 'twin' part — it stays synchronized with the physical chip. If the sensors say the temperature is rising faster than the model predicted, the twin adjusts its internal state.
Luna: And this is all happening on-chip. No cloud round-trip, no latency.
Lucas: Exactly. That's critical for applications where milliseconds matter. Take a data center GPU running a large language model. Power delivery is pushed to the limit. An on-chip digital twin can detect a hot spot forming and reduce the clock on that specific core before the temperature even reaches a dangerous level — proactively, not reactively.
Luna: That's a lot smarter than today's approach, which is usually just throttling everything when a single sensor trips.
Lucas: Exactly. Today's thermal management is coarse. You have a few thermal diodes, and if one hits a threshold, you cut performance across the whole chip. A digital twin gives you fine-grained, predictive control. You can keep the chip running closer to its thermal limit safely, which means better sustained performance.
Luna: Are there any commercial chips shipping with this yet? Or is it still in research?
Lucas: It's mostly in research and early prototyping. Imec's test chip is from 2025. I know of at least one major server CPU vendor that has a team working on integrating a thermal digital twin for their next-generation parts, but they haven't announced it publicly. I expect we'll see production chips with on-chip digital twins by 2028 or 2029.
Luna: One thing I'm wondering — if the twin is running on the same silicon, what happens if the twin itself has a bug? Could it cause the chip to misbehave?
Lucas: That's a real concern. The twin has to be verified just as rigorously as any other on-chip logic. And because it's a model, it's inherently an approximation, so there's always a risk of divergence from reality. The synchronization loop — comparing twin predictions to actual sensor readings — is designed to catch that. But if the sensor itself is faulty, you have a problem. I think we'll see redundancy built in: maybe two independent twins running concurrently.
Luna: Or a twin that monitors the twin? Getting very Inception.
Lucas: Right. But the beauty is that the twin is software — it can be updated. If a bug is found, you can patch the twin's firmware. That's something you can't do with hardware sensors.
Luna: That's a good point. So it adds flexibility. And I imagine the same twin could be repurposed for different optimization goals — like minimizing power one day, maximizing performance another.
Lucas: Exactly. The same reduced model can be used for multiple objectives. The control policy — what you do with the twin's predictions — can be changed via software. So a chip deployed in a data center could initially be tuned for performance, and later re-tuned for energy efficiency as electricity prices change.
Luna: If today's tech conversation gave you something usable — maybe a new perspective on what's coming in chip design — that's the whole point of this show. We deliberately keep these episodes ad-free because we think the topic deserves a clean, focused treatment. If you want to support that approach, the link is buy me a coffee dot com slash fexingo. No pressure, just a way to keep it independent.
Lucas: Yeah, and we genuinely appreciate every listener who does. It lets us spend time on deep dives like this one instead of worrying about ad inventory.
Luna: Alright, back to the tech. I want to dig into how these reduced models are created. You mentioned machine learning — can you give a concrete example of how that works?
Lucas: Sure. Say you have a full 3D thermal model of a processor with 100,000 mesh nodes. You run a bunch of simulations with different power maps — different cores active at different frequencies — and record the resulting temperature at each node. That gives you a training dataset. Then you train a neural network or a linear dynamical system to map power inputs to temperature outputs with high accuracy but far fewer parameters. The resulting model might have only 500 parameters instead of 100,000 nodes.
Luna: And that 500-parameter model is what goes onto the chip?
Lucas: Yes. And it runs in microseconds. The imec chip used a technique called proper orthogonal decomposition combined with a neural network for the nonlinear dynamics. Their model had about 800 floating-point coefficients, stored in on-chip SRAM. The inference engine was a small dedicated accelerator — maybe 50,000 gates.
Luna: That's tiny. So the twin doesn't need a lot of hardware.
Lucas: Right. That's why it's feasible. The accelerator is specialized for solving the reduced model's equations — basically a small linear algebra engine. It's not a general-purpose CPU running Python. It's a fixed-function block that does one thing fast and efficiently.
Luna: And the same approach could be used for other physical phenomena — not just temperature, but voltage droop, mechanical stress, even aging.
Lucas: Exactly. In fact, the imec chip also included a twin for electromigration — the gradual movement of metal atoms in the interconnects that eventually causes open circuits. The twin predicted the remaining useful life of each interconnect tree and dynamically reduced current density in stressed lines.
Luna: That's wild. So the chip is literally managing its own wear and tear in real time.
Lucas: Yes. And that could be revolutionary for applications where you need guaranteed lifetimes — say, a satellite chip that has to operate for 15 years without maintenance. Or a chip in a medical implant where replacement is surgery.
Luna: Is there a limit to how many twins you can put on one chip? Could you have separate twins for temperature, stress, aging, power?
Lucas: You could, but there's a trade-off. Each twin consumes area and power. A better approach is to have a single multi-physics twin that models several phenomena simultaneously, because they are coupled — temperature affects electromigration, voltage affects temperature, etc. That unified twin is more complex but more accurate.
Luna: So the trend is toward one holistic digital twin for the entire chip?
Lucas: That's the goal for the next decade. Early work from researchers at Stanford and UC Berkeley has shown that a unified reduced-order model covering thermal, electrical, and mechanical behavior is feasible for a small processor. Scaling it to a many-core chip with billions of transistors is an open challenge.
Luna: It sounds like we're moving from chips that are designed once and then static, to chips that continuously adapt based on a model of themselves.
Lucas: Exactly. It's a shift from open-loop design to closed-loop operation. And the digital twin is the key enabler. I think in ten years, we'll look back at chips without on-chip twins the way we look at cars without engine management computers — primitive and inefficient.
Luna: That's a strong statement. Let's leave listeners with that image. Thanks, Lucas.
Lucas: Thanks, Luna. See you next time.

Shows are listed from Apple Podcasts' charts and directory, and Podcast Index where it is used. Every show and episode belongs to its publisher and plays from the publisher's own feed; this site hosts none of them.