# Design and Analysis of VLSI Subsystems

- Institution: IIIT Bangalore
- Department: Electronics & Communication Engineering
- Teacher: Prof. Madhav Rao
- Level: Undergraduate
- Language: English
- Subjects: Engineering, Society and politics
- Source: [NPTEL](https://nptel.ac.in/courses/117106149)
- Licence: [CC BY-NC-SA](https://nptel.ac.in/faq) (Non-commercial use only.)
- Syllabus: [at the source](https://nptel.ac.in/courses/117106149)
- Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

## Lectures

1. [1.1 - Understanding Silicon](https://invisiblenetwork.ai/learn/nptel/117106149/5d7dafa782c4) (Video)
2. [1.2 - Introduction to NMOS](https://invisiblenetwork.ai/learn/nptel/117106149/adba72084d7f) (Video)
3. [1.3 - NMOS Transistor Working](https://invisiblenetwork.ai/learn/nptel/117106149/0cf6d25e15aa) (Video)
4. [1.4 - PMOS Transistor](https://invisiblenetwork.ai/learn/nptel/117106149/fadad4715b79) (Video)
5. [1.5 - MOS Capacitances](https://invisiblenetwork.ai/learn/nptel/117106149/3889d60176ee) (Video)
6. [1.6 - Non Ideal MOS model](https://invisiblenetwork.ai/learn/nptel/117106149/af42ea0dbf14) (Video)
7. [1.7 - Short channel current model](https://invisiblenetwork.ai/learn/nptel/117106149/24fd7300eca2) (Video)
8. [1.8 - Short channel current model analysis](https://invisiblenetwork.ai/learn/nptel/117106149/6d9940e524c4) (Video)
9. [2.1 - Channel Length modulation index](https://invisiblenetwork.ai/learn/nptel/117106149/3c7b7a706d4b) (Video)
10. [2.2 - DC characteristics of Inverter](https://invisiblenetwork.ai/learn/nptel/117106149/d3942218bfe2) (Video)
11. [2.3 - Transfer characteristics of Inverter](https://invisiblenetwork.ai/learn/nptel/117106149/07aeb632322d) (Video)
12. [2.4 - Skewed Inverter](https://invisiblenetwork.ai/learn/nptel/117106149/7ce16b657749) (Video)
13. [2.5 - Skewed Inverter and threshold voltage](https://invisiblenetwork.ai/learn/nptel/117106149/92df9c7285b9) (Video)
14. [2.6 - Equivalent of transistors in series](https://invisiblenetwork.ai/learn/nptel/117106149/bf794b3ab184) (Video)
15. [2.7 - Transmission Gate](https://invisiblenetwork.ai/learn/nptel/117106149/2260a2b58d9c) (Video)
16. [3.1 - Bad CMOS Buffer - Part1](https://invisiblenetwork.ai/learn/nptel/117106149/a4def2eed46a) (Video)
17. [3.2 - Bad CMOS Buffer - Part2](https://invisiblenetwork.ai/learn/nptel/117106149/48e6f0496716) (Video)
18. [3.3 - Noise margin characteristics of inverter](https://invisiblenetwork.ai/learn/nptel/117106149/d1b42e2672f8) (Video)
19. [3.4 - Noise margin parameters](https://invisiblenetwork.ai/learn/nptel/117106149/ad78d0f32a4a) (Video)
20. [3.5 - Introduction to Delay in CMOS](https://invisiblenetwork.ai/learn/nptel/117106149/a6f3f187cecc) (Video)
21. [3.6 - Transient analysis of CMOS Inverter](https://invisiblenetwork.ai/learn/nptel/117106149/6c42e27ef299) (Video)
22. [3.7 - RC approximated delay](https://invisiblenetwork.ai/learn/nptel/117106149/923e2b9a56f4) (Video)
23. [3.8 - Switching Resistance](https://invisiblenetwork.ai/learn/nptel/117106149/46f7c36a9cd4) (Video)
24. [4.1 - CMOS Inverter approximated to RC Circuit](https://invisiblenetwork.ai/learn/nptel/117106149/73f0ef02ea7b) (Video)
25. [4.2 - Elmore delay](https://invisiblenetwork.ai/learn/nptel/117106149/e0b588ae63ab) (Video)
26. [4.3 - Delay of FO4 inverter](https://invisiblenetwork.ai/learn/nptel/117106149/6a52435fb445) (Video)
27. [4.4 - Extracting capacitances of 3-Nand gate for delay estimation](https://invisiblenetwork.ai/learn/nptel/117106149/c76663b8baf3) (Video)
28. [4.5 - Characterizing Delay of NOR gate](https://invisiblenetwork.ai/learn/nptel/117106149/079c26a7fbca) (Video)
29. [4.6 - Linear Delay model](https://invisiblenetwork.ai/learn/nptel/117106149/b02c8027bbcb) (Video)
30. [4.7 - Logical effort and Parasitic delay](https://invisiblenetwork.ai/learn/nptel/117106149/a2b96e5c231c) (Video)
31. [5.1 - Logical effort and Parasitic delay for different gates](https://invisiblenetwork.ai/learn/nptel/117106149/7fb1ebcd940f) (Video)
32. [5.2 - Logical effort for short-channel current model](https://invisiblenetwork.ai/learn/nptel/117106149/2a20f6e39366) (Video)
33. [5.3 - Ring Oscillator design](https://invisiblenetwork.ai/learn/nptel/117106149/98a380fdec5f) (Video)
34. [5.4 - Optimizing Gate Size](https://invisiblenetwork.ai/learn/nptel/117106149/c1b6d94b286f) (Video)
35. [5.5 - Optimizing Gate Sizes Example](https://invisiblenetwork.ai/learn/nptel/117106149/c27127ca834e) (Video)
36. [5.6 - Optimizing the Stages for an inverter path](https://invisiblenetwork.ai/learn/nptel/117106149/ca90f1aaa5ae) (Video)
37. [5.7 - Optimizing the Stages for a General Circuit](https://invisiblenetwork.ai/learn/nptel/117106149/a4d0d873caaf) (Video)
38. [5.8 - Decoder Design](https://invisiblenetwork.ai/learn/nptel/117106149/90d40ce63d08) (Video)
39. [6.1 - Introduction to Combinational Circuit and assymetric gates](https://invisiblenetwork.ai/learn/nptel/117106149/55bfa341896b) (Video)
40. [6.2 - Assymetric Gates analysis](https://invisiblenetwork.ai/learn/nptel/117106149/5ef3078c56eb) (Video)
41. [6.3 - Assymetric Gates analysis using short-channel current model](https://invisiblenetwork.ai/learn/nptel/117106149/c3d771c9cf59) (Video)
42. [6.4 - Introduction to Skewed gates](https://invisiblenetwork.ai/learn/nptel/117106149/c67a13d130d6) (Video)
43. [6.5 - Skewed gates and best P/N ratio](https://invisiblenetwork.ai/learn/nptel/117106149/eaa8ba251ed4) (Video)
44. [6.6 - vIntroduction to Pseudo NMOS](https://invisiblenetwork.ai/learn/nptel/117106149/e7047871cb94) (Video)
45. [6.7 - Psudeo NMOS gates](https://invisiblenetwork.ai/learn/nptel/117106149/c92532681e42) (Video)
46. [6.8 - Other Logic Family](https://invisiblenetwork.ai/learn/nptel/117106149/4ced102ae17c) (Video)
47. [6.9 - Dynamic Logic and Domino logic](https://invisiblenetwork.ai/learn/nptel/117106149/e36ae805bad4) (Video)
48. [7.1 - Domino gates](https://invisiblenetwork.ai/learn/nptel/117106149/ad4debfaa473) (Video)
49. [7.2 - Introduction to Stick Diagram](https://invisiblenetwork.ai/learn/nptel/117106149/d2ff78d65331) (Video)
50. [7.3 - Stick Diagram for different gates](https://invisiblenetwork.ai/learn/nptel/117106149/0803b841b589) (Video)
51. [7.4 - Applying Eulers path for stick diagram representations](https://invisiblenetwork.ai/learn/nptel/117106149/d15a6827b2fb) (Video)
52. [7.5 - Multiplexer design and layout](https://invisiblenetwork.ai/learn/nptel/117106149/473b121a5494) (Video)
53. [7.6 - Introduction to Interconnects](https://invisiblenetwork.ai/learn/nptel/117106149/16e2819c5f33) (Video)
54. [7.7 - Interconnects - RC delay, and Energy](https://invisiblenetwork.ai/learn/nptel/117106149/17b419207fe6) (Video)
55. [8.1 - Introduction to crosstalks in interconnects](https://invisiblenetwork.ai/learn/nptel/117106149/2df0fa6a2987) (Video)
56. [8.2 - Transient analysis in Crosstalk](https://invisiblenetwork.ai/learn/nptel/117106149/d0bdb2a473b5) (Video)
57. [8.3 - Introduction to Repeaters in Interconnect Engineering](https://invisiblenetwork.ai/learn/nptel/117106149/cb84e498771b) (Video)
58. [8.4 - Repeater Design](https://invisiblenetwork.ai/learn/nptel/117106149/1f2109fff35e) (Video)
59. [8.5 - Energy and delay analysis for interconnectwith repeaters](https://invisiblenetwork.ai/learn/nptel/117106149/7451fc16dd6b) (Video)
60. [8.6 - Repeater Design and Energy-Delay-Product](https://invisiblenetwork.ai/learn/nptel/117106149/5eb0365e464d) (Video)
61. [8.7 - Introduction to Power](https://invisiblenetwork.ai/learn/nptel/117106149/46e4f0794f13) (Video)
62. [9.1 - Switching Power and Energy Estimation](https://invisiblenetwork.ai/learn/nptel/117106149/b97da1dd43f2) (Video)
63. [9.2 - Activity factor and estimating dynamic power for a combinational circuit design](https://invisiblenetwork.ai/learn/nptel/117106149/bf99d9a78023) (Video)
64. [9.3 - Analyzing Dynamic Power](https://invisiblenetwork.ai/learn/nptel/117106149/c4c5102dceac) (Video)
65. [9.4 - Energy estimation through driving factor](https://invisiblenetwork.ai/learn/nptel/117106149/00521b0375d9) (Video)
66. [9.5 - Energy expression in terms of delay](https://invisiblenetwork.ai/learn/nptel/117106149/a21b88de7508) (Video)
67. [9.6 - Voltage Scaling](https://invisiblenetwork.ai/learn/nptel/117106149/bb973b66b336) (Video)
68. [9.7 - DVFS](https://invisiblenetwork.ai/learn/nptel/117106149/a965539ce15f) (Video)
69. [10.1 - Introduction to subthreshold leakage current model](https://invisiblenetwork.ai/learn/nptel/117106149/777e8396cfea) (Video)
70. [10.2 - Subthreshold leakage current and Gate leakage current](https://invisiblenetwork.ai/learn/nptel/117106149/fe56609b55d9) (Video)
71. [10.3 - Estimating Static Power](https://invisiblenetwork.ai/learn/nptel/117106149/8bde0445cc19) (Video)
72. [10.4 - Introduction to CMOS Latch design](https://invisiblenetwork.ai/learn/nptel/117106149/0ed876f25450) (Video)
73. [10.5 - CMOS Latch Design](https://invisiblenetwork.ai/learn/nptel/117106149/da1390643d7f) (Video)
74. [10.6 - CMOS Latch and flipflop design](https://invisiblenetwork.ai/learn/nptel/117106149/a0a981cd4911) (Video)
75. [11.1 - Static Timing Analysis](https://invisiblenetwork.ai/learn/nptel/117106149/e27d21a70c69) (Video)
76. [11.2 - Static Timing Analysis - Continued](https://invisiblenetwork.ai/learn/nptel/117106149/aee3d974a1cd) (Video)
77. [11.3 - Static Timing Analysis - Part2](https://invisiblenetwork.ai/learn/nptel/117106149/e7cddfd31681) (Video)
78. [11.4 - Static Timing Analysis - Part2.1](https://invisiblenetwork.ai/learn/nptel/117106149/ed3dbc245f2f) (Video)
79. [11.5 - Static Timing Analysis - Part3](https://invisiblenetwork.ai/learn/nptel/117106149/7b36f783080a) (Video)
80. [11.6 - TPDQ and TPCQ](https://invisiblenetwork.ai/learn/nptel/117106149/be9415340636) (Video)
81. [11.7 - Static Timing Analysis - Part4](https://invisiblenetwork.ai/learn/nptel/117106149/4b9abc407d79) (Video)
82. [11.8 - Static Timing Analysis - Part5](https://invisiblenetwork.ai/learn/nptel/117106149/5adf7c8a187e) (Video)
83. [11.9 - Static Timing Analysis - Part6](https://invisiblenetwork.ai/learn/nptel/117106149/a8f6d5125cd1) (Video)
84. [11.10 - SET and CLEAR enabled Latch and Flipflop Design](https://invisiblenetwork.ai/learn/nptel/117106149/4e1f9970757a) (Video)
85. [12.1 - 1-bit Adder design](https://invisiblenetwork.ai/learn/nptel/117106149/8c997ddb9bb5) (Video)
86. [12.2 - Adder-Part2](https://invisiblenetwork.ai/learn/nptel/117106149/275f45666b8b) (Video)
87. [12.3 - PG architecture - Part1](https://invisiblenetwork.ai/learn/nptel/117106149/5d883a5a20c8) (Video)
88. [12.4 - PG architecture - Part2](https://invisiblenetwork.ai/learn/nptel/117106149/67fb5f5caac7) (Video)
89. [12.5 - Carry Skip Adder](https://invisiblenetwork.ai/learn/nptel/117106149/1774832ada93) (Video)
90. [12.6 - Carry Look Ahead and Carry Increment Adder](https://invisiblenetwork.ai/learn/nptel/117106149/ce61294b0c65) (Video)
91. [12.7 - Other Adder Subsystems](https://invisiblenetwork.ai/learn/nptel/117106149/c73807ef039a) (Video)
92. [12.8 - Approximate Multipliers - Part 1](https://invisiblenetwork.ai/learn/nptel/117106149/c3b7b82770bc) (Video)
93. [12.9 - Approximate Multipliers - Part 2](https://invisiblenetwork.ai/learn/nptel/117106149/451f904982ae) (Video)
94. [12.10 - Approximate Adder](https://invisiblenetwork.ai/learn/nptel/117106149/d62f42b3743f) (Video)
95. [Live Session 26-02-2022](https://invisiblenetwork.ai/learn/nptel/117106149/5d7dafa782c4-2) (Video)