# Hardware Modeling using Verilog

- Institution: IIT Kharagpur
- Department: Computer Science and Engineering
- Teacher: Prof. Indranil Sengupta
- Level: Undergraduate
- Language: English
- Subjects: Computer science, Engineering
- Source: [NPTEL](https://nptel.ac.in/courses/106105165)
- Licence: [CC BY-NC-SA](https://nptel.ac.in/faq) (Non-commercial use only.)
- Syllabus: [at the source](https://nptel.ac.in/courses/106105165)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

The course will introduce the participants to the Verilog hardware description language. It will help them to learn various digital circuit modeling issues using Verilog, writing test benches, and some case studies.

Intended audience: Computer Science and Engineering ; Electronics and Communication Engineering ; Electrical Engineering

Prerequisites: Basic concepts in digital circuit design ; Familiarity with a programming language like C or C++

## Lectures

1. [Lecture 1: Introduction](https://invisiblenetwork.ai/learn/nptel/106105165/7ce04b9f32a4) (YouTube)
2. [Lecture 2 : Design Representation](https://invisiblenetwork.ai/learn/nptel/106105165/1aea7857d178) (YouTube)
3. [Lecture 3 : Getting Started with Verilog](https://invisiblenetwork.ai/learn/nptel/106105165/6f8772cb528b) (YouTube)
4. [Lecture 4: VLSI Design Styles (Part 1)](https://invisiblenetwork.ai/learn/nptel/106105165/8df9476b1e98) (YouTube)
5. [Lecture 5 : VLSI Design Styles (Part 2)](https://invisiblenetwork.ai/learn/nptel/106105165/1b32845b5521) (YouTube)
6. [Lecture 6: VERILOG LANGUAGE FEATURES (PART 1)](https://invisiblenetwork.ai/learn/nptel/106105165/6c83dc419a19) (YouTube)
7. [Lecture 7: VERILOG LANGUAGE FEATURES (PART 2)](https://invisiblenetwork.ai/learn/nptel/106105165/f202f518f1a0) (YouTube)
8. [Lecture 8: VERILOG LANGUAGE FEATURES (PART 3)](https://invisiblenetwork.ai/learn/nptel/106105165/37d707c48614) (YouTube)
9. [Lecture 9: VERILOG OPERATORS](https://invisiblenetwork.ai/learn/nptel/106105165/9413acd71fc3) (YouTube)
10. [Lecture 10: VERILOG MODELING EXAMPLES](https://invisiblenetwork.ai/learn/nptel/106105165/f9e1c3338602) (YouTube)
11. [Lecture 11: VERILOG MODELING EXAMPLES (Contd)](https://invisiblenetwork.ai/learn/nptel/106105165/f71553d5fcb5) (YouTube)
12. [Lecture 12: VERILOG DESCRIPTION STYLES](https://invisiblenetwork.ai/learn/nptel/106105165/ade1fe822c72) (YouTube)
13. [Lecture 13: PROCEDURAL ASSIGNMENT](https://invisiblenetwork.ai/learn/nptel/106105165/92e80b5fdc1f) (YouTube)
14. [Lecture 14: PROCEDURAL ASSIGNMENT (Contd.)](https://invisiblenetwork.ai/learn/nptel/106105165/866a271fcdef) (YouTube)
15. [Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES)](https://invisiblenetwork.ai/learn/nptel/106105165/3b889505398d) (YouTube)
16. [Lecture 16: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 1)](https://invisiblenetwork.ai/learn/nptel/106105165/0157841a73f6) (YouTube)
17. [Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)](https://invisiblenetwork.ai/learn/nptel/106105165/68502a0e1877) (YouTube)
18. [Lecture 18: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)](https://invisiblenetwork.ai/learn/nptel/106105165/4fbb65ac0055) (YouTube)
19. [Lecture 19: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)](https://invisiblenetwork.ai/learn/nptel/106105165/56cc68e016f3) (YouTube)
20. [Lecture 20: USER DEFINED PRIMITIVES](https://invisiblenetwork.ai/learn/nptel/106105165/820fa819ebf9) (YouTube)
21. [Lecture 21 : VERILOG TEST BENCH](https://invisiblenetwork.ai/learn/nptel/106105165/d28c73a04995) (YouTube)
22. [Lecture 22 : WRITING VERILOG TEST BENCHES](https://invisiblenetwork.ai/learn/nptel/106105165/89fb887386f1) (YouTube)
23. [Lecture 23 : MODELING FINITE STATE MACHINES](https://invisiblenetwork.ai/learn/nptel/106105165/31521498ec55) (YouTube)
24. [Lecture 24 : MODELING FINITE STATE MACHINES (Contd.)](https://invisiblenetwork.ai/learn/nptel/106105165/26a52558ae36) (YouTube)
25. [Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1)](https://invisiblenetwork.ai/learn/nptel/106105165/03e917236347) (YouTube)
26. [Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2)](https://invisiblenetwork.ai/learn/nptel/106105165/ceed48e93cbc) (YouTube)
27. [Lecture 27 : DATAPATH AND CONTROLLER DESIGN (PART 3)](https://invisiblenetwork.ai/learn/nptel/106105165/2611f58dbd3f) (YouTube)
28. [Lecture 28 : SYNTHESIZABLE VERILOG](https://invisiblenetwork.ai/learn/nptel/106105165/85c5cbe0eb52) (YouTube)
29. [Lecture 29 : SOME RECOMMENDED PRACTICES](https://invisiblenetwork.ai/learn/nptel/106105165/3748d919a82f) (YouTube)
30. [Lecture 30 : MODELING MEMORY](https://invisiblenetwork.ai/learn/nptel/106105165/36c2aac1180b) (YouTube)
31. [Lecture 31 : MODELING REGISTER BANKS](https://invisiblenetwork.ai/learn/nptel/106105165/1a81c066e183) (YouTube)
32. [Lecture 32 : BASIC PIPELINING CONCEPTS](https://invisiblenetwork.ai/learn/nptel/106105165/ac1fe947bb68) (YouTube)
33. [Lecture 33 : PIPELINE MODELING (PART 1)](https://invisiblenetwork.ai/learn/nptel/106105165/5669a51a74ad) (YouTube)
34. [Lecture 34 : PIPELINE MODELING (PART 2)](https://invisiblenetwork.ai/learn/nptel/106105165/96744fc55fb4) (YouTube)
35. [Lecture 35 : SWITCH LEVEL MODELING (PART 1)](https://invisiblenetwork.ai/learn/nptel/106105165/0e51846355bf) (YouTube)
36. [Lecture 36 : SWITCH LEVEL MODELING (PART 2)](https://invisiblenetwork.ai/learn/nptel/106105165/f2d262bc3bc2) (YouTube)
37. [Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)](https://invisiblenetwork.ai/learn/nptel/106105165/89922d950605) (YouTube)
38. [Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)](https://invisiblenetwork.ai/learn/nptel/106105165/0db277b47326) (YouTube)
39. [Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)](https://invisiblenetwork.ai/learn/nptel/106105165/65f46ebb80d9) (YouTube)
40. [Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1)](https://invisiblenetwork.ai/learn/nptel/106105165/8b93e321db39) (YouTube)
41. [Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2)](https://invisiblenetwork.ai/learn/nptel/106105165/ef5afefcc1dc) (YouTube)