# Synthesis of Digital Systems

- Institution: IIT Delhi
- Department: Computer Science and Engineering
- Teacher: Prof. Preeti Ranjan Panda
- Level: Undergraduate
- Language: English
- Subjects: Computer science, Engineering
- Source: [NPTEL](https://nptel.ac.in/courses/106102181)
- Licence: [CC BY-NC-SA](https://nptel.ac.in/faq) (Non-commercial use only.)
- Syllabus: [at the source](https://nptel.ac.in/courses/106102181)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

## Lectures

1. [Outline - What is Synthesis?](https://invisiblenetwork.ai/learn/nptel/106102181/68a93184b244) (Video)
2. [Chip Design Flow and Hardware Modelling](https://invisiblenetwork.ai/learn/nptel/106102181/af28559bcc83) (Video)
3. [VHDL: Introduction to Hardware Description Languages & VHDL Basics](https://invisiblenetwork.ai/learn/nptel/106102181/47a9941237c4) (Video)
4. [VHDL: Modelling Timing - Events & Transactions](https://invisiblenetwork.ai/learn/nptel/106102181/058b1d084386) (Video)
5. [VHDL: Specifying Hardware Behaviour with Processes](https://invisiblenetwork.ai/learn/nptel/106102181/1b2b576aed4e) (Video)
6. [VHDL: Specifying Structure, Test Benches, Parameterisation, & Libraries](https://invisiblenetwork.ai/learn/nptel/106102181/f2167013eaf4) (Video)
7. [Introduction to High-level Synthesis](https://invisiblenetwork.ai/learn/nptel/106102181/4017a306f999) (Video)
8. [Language front-end Design Representation](https://invisiblenetwork.ai/learn/nptel/106102181/18747132fdb7) (Video)
9. [Compiler Transformation in High Level Synthesis: Constant Folding, Dead Code Elimination, Constant Propagation, & Strength Reduction](https://invisiblenetwork.ai/learn/nptel/106102181/9839b109434a) (Video)
10. [Memory Modelling & Compiler Transformation in High Level Synthesis: Common Sub-expression Elimination & Loop Invariant Code Motion](https://invisiblenetwork.ai/learn/nptel/106102181/5c17af51bf0a) (Video)
11. [Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining](https://invisiblenetwork.ai/learn/nptel/106102181/1ec06c064c78) (Video)
12. [Hardware Transformations & ASAP / ALAP Scheduling](https://invisiblenetwork.ai/learn/nptel/106102181/0a8dc3e8878b) (Video)
13. [Scheduling in High Level Synthesis: List Scheduling & Time-constrained Scheduling](https://invisiblenetwork.ai/learn/nptel/106102181/0b66e9c2bed7) (Video)
14. [Force Directed Scheduling & Register Allocation](https://invisiblenetwork.ai/learn/nptel/106102181/79990a86d842) (Video)
15. [High Level Synthesis and Timing Issues](https://invisiblenetwork.ai/learn/nptel/106102181/e619475e0c4b) (Video)
16. [Finite State Machine Synthesis: Introduction to FSM Encoding](https://invisiblenetwork.ai/learn/nptel/106102181/7e097e492783) (Video)
17. [Finite State Machine Synthesis: Identifyinh Common Cubes & Graph Embedding](https://invisiblenetwork.ai/learn/nptel/106102181/b9ef670af0e5) (Video)
18. [The Retiming Problem](https://invisiblenetwork.ai/learn/nptel/106102181/29ea2764ec77) (Video)
19. [Efficient Solution to Retiming & Introduction to Logic Synthesis](https://invisiblenetwork.ai/learn/nptel/106102181/4f863d4b80b6) (Video)
20. [Binary Decision Diagrams](https://invisiblenetwork.ai/learn/nptel/106102181/cec877af623c) (Video)
21. [Introduction to Logic Synthesis](https://invisiblenetwork.ai/learn/nptel/106102181/a1fdcc0a96b5) (Video)
22. [Two-level Logic Optimisation](https://invisiblenetwork.ai/learn/nptel/106102181/a36d252cb073) (Video)
23. [Multi-Level Logic Optimisation](https://invisiblenetwork.ai/learn/nptel/106102181/fbb548d76d61) (Video)
24. [Multi-level Logic Synthesis: Technology Mapping](https://invisiblenetwork.ai/learn/nptel/106102181/2f4d04304de3) (Video)
25. [Introduction to Timing Analysis](https://invisiblenetwork.ai/learn/nptel/106102181/7afdf7744f75) (Video)
26. [Timing Analysis & Critical Paths](https://invisiblenetwork.ai/learn/nptel/106102181/f4adf8a98fce) (Video)