# Latency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC

- Institution: CERN
- Speaker: Valerio Nappi
- Year: 2026
- Language: English
- Subjects: Mathematics
- Source: [CERN](https://videos.cern.ch/record/3025787)
- Licence: [CERN](https://copyright.web.cern)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

Real-time control algorithms for power converters in particle accelerators require flexible platforms capable of high iteration rates (up to 100 kHz). This work evaluates the suitability of the Zynq UltraScale+ SoC (A53 cores) for such applications. After characterizing the access time of the most basic FPGA-CPU access path, we show how this path is unsuitable for real time controls. We then propose an alternative system, characterizing the critical metrics: PL access, Memory access, ACP latency performance, and Interrupt latency. We identify a suitable data path for real time controls and propose an exploitation paradigm for achieving reliable sub-microsecond latency.

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## Lectures

1. [Latency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC](https://invisiblenetwork.ai/learn/cern/3025787/9ec499495b73), 23 min (CERN's player)