# SystemVerilog Hacks: Circumventing the Limitations of SystemVerilog - Institution: CERN - Speaker: Yair Linn - Year: 2026 - Language: English - Source: [CERN](https://videos.cern.ch/record/3025785) - Licence: [CERN](https://copyright.web.cern) - Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words) SystemVerilog is a powerful language with relatively good compiler support. However, some inexplicable oversights and limitations in the SystemVerilog standard can cause HDL designers to expend significant work that would have been unnecessary had simple tweaks in the language's standard been adopted. For example, one limitation of SystemVerilog is that a "struct" cannot be parameterized more than once, i.e. the same "struct" code needs to be rewritten every time any of the parameters that define it change. A similar issue affects SystemVerilog functions. With regards to SystemVerilog interfaces, a necessary but lacking feature of SystemVerilog would be the ability to propagate parameters directly from an interface to other parts of the code, without needing to pass the parameters themselves up and down the design hierarchy. In this presentation we discuss these and other issues and their workaround solutions that enable the designer to make much more efficient use of SystemVerilog. 00:00:00 Slide 1 00:01:01 Slide 2 00:02:38 Slide 3 00:04:00 Slide 4 00:04:30 Slide 5 00:04:54 Slide 6 00:05:28 Slide 7 00:06:20 Slide 8 00:06:45 Slide 9 00:07:01 Slide 10 00:08:10 Slide 11 00:08:20 Slide 12 00:08:54 Slide 13 00:09:46 Slide 14 00:11:14 Slide 15 00:11:38 Slide 16 00:12:11 Slide 17 00:12:54 Slide 18 00:13:15 Slide 19 00:13:33 Slide 20 00:14:13 Slide 21 00:14:30 Slide 22 00:14:55 Slide 23 00:15:12 Slide 24 00:15:57 Slide 25 00:16:40 Slide 26 00:16:54 Slide 27 00:17:31 Slide 28 ## Lectures 1. [SystemVerilog Hacks: Circumventing the Limitations of SystemVerilog](https://invisiblenetwork.ai/learn/cern/3025785/7334d14c5936), 21 min (CERN's player)