# Dynamic Derandomizing Buffer: A Portable and Scalable Solution for Time-Ordered Packet Aggregation

- Institution: CERN
- Speaker: Mitja Vodnik
- Year: 2026
- Language: English
- Source: [CERN](https://videos.cern.ch/record/3025781)
- Licence: [CERN](https://copyright.web.cern)
- Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

The Dynamic Derandomizing Buffer is a firmware design for joining time-stamped packets form multiple incoming data streams with randomly varying time-skews into a single time-ordered output stream. It is developed at CERN primarily to handle the output from the novel FastRICH ASIC (the LHCb RICH detector readout chip for Runs 4 and 5), but intentionally made agnostic to this use-case so it can be used in any similar real-time stream processing scenario. Written in pure VHDL, it is also fully portable: it was successfully built for both Intel and AMD devices.

This presentation covers a scalable and configurable tree-based aggregation architecture, portable BRAM-based buffering components, and a special time-stamp windowing algorithm which guides the time-ordering process. We also share our experience in applying test-driven development approach (using formal verification and self-testing UVVM-based simulation) to a complex FPGA design.

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## Lectures

1. [Dynamic Derandomizing Buffer: A Portable and Scalable Solution for Time-Ordered Packet Aggregation](https://invisiblenetwork.ai/learn/cern/3025781/8e4e8ae3767b), 31 min (CERN's player)