# Inside UVVM: Architecture and Design of Custom Verification Components

- Institution: CERN
- Speaker: Markus Leiter
- Year: 2026
- Language: English
- Subjects: Art, architecture and design
- Source: [CERN](https://videos.cern.ch/record/3025771)
- Licence: [CERN](https://copyright.web.cern)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

This talk takes an in-depth look inside a UVVM VVC, explaining its internal architecture and core design principles. Key concepts such as the command-based interface, command queue, command interpreter, and executor are explored in detail, along with synchronization mechanisms, transaction handling, and the interaction with Bus Functional Models (BFMs).

Building on this foundation, the presentation demonstrates how to develop custom UVVM-compliant VVCs using the official templates and generator support. Practical guidance and best practices are shared to help attendees design reusable, maintainable, and well-integrated verification components that fit seamlessly into existing UVVM-based testbenches.

The talk is aimed at FPGA developers who are already familiar with the basics of UVVM and want to move beyond using existing VVCs—gaining the confidence to understand, extend, and create their own verification components.

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## Lectures

1. [Inside UVVM: Architecture and Design of Custom Verification Components](https://invisiblenetwork.ai/learn/cern/3025771/5384e24044c0), 29 min (CERN's player)