# Scalable and lightweight RoCEv2 TX FPGA IP core

- Institution: CERN
- Speaker: Gabriele Bortolato
- Year: 2026
- Language: English
- Source: [CERN](https://videos.cern.ch/record/3025763)
- Licence: [CERN](https://copyright.web.cern)
- Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

In many Data Acquisition (DAQ) systems, a significant portion of CPU resources is spent on networking rather than actual data processing. One way to reduce this overhead is to implement Remote Direct Memory Access (RDMA) directly in FPGA logic. Offloading RDMA to hardware can increase throughput, reduce latency, and significantly lower CPU utilization on the receiver side. This talk presents a scalable, portable, and lightweight RoCEv2 FPGA IP core. The architecture is intentionally simplified by removing the RX path and implementing only the TX side, specifically the SEND and RDMA WRITE operations, since FPGA-based DAQ applications typically do not require an RDMA receiver functionality. The IP has been validated at 10/25/100 Gbps on a Xilinx Virtex UltraScale+ FPGA (VCU118) and at 400 Gbps on a Xilinx Versal Premium ACAP (VPK180). We present measured throughput and Round-Trip Time (RTT) results, along with comparisons against NIC-to-NIC RDMA and standard TCP/IP solutions.

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## Lectures

1. [Scalable and lightweight RoCEv2 TX FPGA IP core](https://invisiblenetwork.ai/learn/cern/3025763/c842e3be101b), 29 min (CERN's player)