# Exploring Linearity and Temperature Stability in Time-to-Digital Converters

- Institution: CERN
- Department: FPGA Developers' Forum (FDF)
- Speaker: Gian-Luca Brazerol
- Year: 2025
- Language: English
- Source: [CERN](https://videos.cern.ch/record/3023520)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

High-precision time measurements on the order of picoseconds ($10^{-12}$), as required in fluorescence lifetime microscopy and time-of-flight (ToF) applications, can be achieved using Time-to-Digital Converters (TDCs). Traditional timing methods rely on high-frequency clock counters, which become impractical for such small time intervals. A solution is to exploit the hardware of FPGAs to achieve sub-clock time resolutions. Although much of the existing literature on TDCs focuses on minimizing resolution while maintaining accuracy, the linearity and temperature dependence on performance is often overlooked. These factors are strongly tied to the underlying fabrication technology and hardware architecture. This presentation explores a Tapped-Delay-Line (TDL) TDC design implemented across different FPGA families (AMD, Efinix, Intel), with an emphasis on their linearity and temperature dependency, highlighting the performance differences and considerations for practical applications..

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## Lectures

1. [Exploring Linearity and Temperature Stability in Time-to-Digital Converters](https://invisiblenetwork.ai/learn/cern/3023520/df7f09d3d0f7), 31 min (CERN's player)