# Error-Redundant Implementation of Commercial IP Cores: A Practical Example

- Institution: CERN
- Department: FPGA Developers' Forum (FDF)
- Speaker: Philipp Jacobsohn
- Year: 2025
- Language: English
- Source: [CERN](https://videos.cern.ch/record/3023499)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

The reuse of predefined IP cores is a well-established practice in semiconductor design, offering cost and technical advantages. However, commercial providers must meet diverse implementation requirements, ensuring compliance with specifications while optimizing power, frequency, gate utilization, and feature scope. Additionally, IP cores must function reliably across FPGA and ASIC platforms, often under harsh conditions. Fault tolerance demands techniques like triple-mode redundancy, error correction codes, and fail-safe state machines—but the greater challenge lies in verification and validation. These processes are time-intensive and costly, especially for third-party certification. This paper presents a case study on implementing, verifying, and validating a PSI5 Controller IP core developed by SmartDV to meet ASIL-B certification under ISO 26262. It highlights key challenges and best practices for designing error-redundant IP cores..

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## Lectures

1. [Error-Redundant Implementation of Commercial IP Cores: A Practical Example](https://invisiblenetwork.ai/learn/cern/3023499/748dbeada94d), 23 min (CERN's player)