# Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers

- Institution: CERN
- Department: FPGA Developers' Forum (FDF)
- Speaker: Paul Bachek
- Year: 2025
- Language: English
- Source: [CERN](https://videos.cern.ch/record/3022289)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

The Electron Ion Collider (EIC) Timing Data Link requires high precision clock recovery for accelerator master clock distribution. To meet the performance requirements a novel method for extracting a low jitter data frame clock from serial encoded data using Xilinx Ultrascale+ transceivers is presented. The frame clock frequency is at the word rate of the serial data link and its phase is deterministic. Dedicated FPGA output pins are used to eliminate phase drift from routing variations and minimize the effects of process, voltage, and temperature (PVT). This method enables timing endpoints to recover the accelerator master clock with minimal added phase noise..

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## Lectures

1. [Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers](https://invisiblenetwork.ai/learn/cern/3022289/98096c9777c4), 25 min (CERN's player)