# Data Processing with FPGAs: Parallel Computing on Compact Configurable Logic

- Institution: CERN
- Department: Inverted CSC
- Speaker: Peter Hinderberger
- Year: 2025
- Language: English
- Subjects: Computer science
- Source: [CERN](https://videos.cern.ch/record/3022214)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

In particle physics, Field-Programmable Gate Arrays (FPGAs) play an increasing role in acquiring, processing, and filtering data at experiments with high data rates. Today their advanced technology allows for complex processing, rather than just being used as glue logic on the hardware level. The high degree of parallelism, flexibility, and number of IOs in combination with low power consumption and size make them a valid choice for many applications in science and industry.

A drawback is the high complexity of designing efficient and optimized firmware using Hardware Description Languages (HDL). High-Level Synthesis (HLS) approaches, however, gain more and more popularity. They allow for comparatively simple and effective implementation of complex algorithms, for example in real-time image processing or deep learning.

In this lecture, I will discuss how FPGAs operate, their building blocks, properties, advantages, challenges, and general feasibility in an experimental context. I will go through the general process of designing logic on the RTL level with a beginner-friendly code example to provide a more tangible treatment. Recent developments, comparisons to other widely used computing architectures, and exemplary use cases will conclude with a short view of HLS as an alternative approach suitable for software engineers..

0:00:00 Slide 1

0:01:26 Slide 2

0:02:38 Slide 3

0:05:39 Slide 4

0:07:30 Slide 5

0:09:01 Slide 6

0:10:04 Slide 7

0:12:17 Slide 8

0:21:23 Slide 9

0:22:50 Slide 10

0:24:10 Slide 11

0:25:19 Slide 12

0:26:40 Slide 13

0:28:18 Slide 14

0:30:46 Slide 15

0:32:40 Slide 16

0:35:57 Slide 17

0:38:01 Slide 18

0:40:55 Slide 19

0:42:05 Slide 20

0:43:52 Slide 21

0:46:24 Slide 22

0:48:00 Slide 23

0:49:43 Slide 24

0:51:51 Slide 25

## Lectures

1. [Data Processing with FPGAs: Parallel Computing on Compact Configurable Logic](https://invisiblenetwork.ai/learn/cern/3022214/6d21bc832975), 57 min (CERN's player)