# Why Your Team Should be using VHDL + OSVVM for Verification

- Institution: CERN
- Department: FPGA Developers' Forum (FDF)
- Speaker: Jim Lewis
- Year: 2025
- Language: English
- Source: [CERN](https://videos.cern.ch/record/3021516)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

Developing and deploying a verification methodology is costly and time consuming. Going without one is even more costly due to bugs escaping into production hardware systems.

Open Source VHDL Verification Methodology (OSVVM) provides the VHDL community with verification capabilities that rival any other verification methodology – including SystemVerilog + UVM. Yet OSVVM is easier as it allows any VHDL engineer to write VHDL testbenches, test cases, and verification components for both simple unit/RTL level tests and complex, randomized full chip or system level tests.

With OSVVM you get transaction-based testing, a verification framework, verification components, self-checking tests, messaging handling, error tracking, requirements tracking, constrained random testing, scoreboards, functional coverage, co-simulation with software, test automation, scripts, and a comprehensive set of test reports.

This presentation examines the benefits of using OSVVM on your projects..

0:00:00 Slide 1

0:01:40 Slide 2

0:05:34 Slide 3

0:06:50 Slide 4

0:09:00 Slide 5

0:10:57 Slide 6

0:12:41 Slide 7

0:14:50 Slide 8

0:16:19 Slide 9

0:17:30 Slide 10

0:19:00 Slide 11

0:23:08 Slide 12

0:26:33 Slide 13

## Lectures

1. [Why Your Team Should be using VHDL + OSVVM for Verification](https://invisiblenetwork.ai/learn/cern/3021516/f44958d37e93), 43 min (CERN's player)