# Architecting FPGA for low power Leadership

- Institution: CERN
- Department: FPGA Developers' Forum (FDF)
- Speaker: Hardik Shah
- Year: 2025
- Language: English
- Subjects: Business and management
- Source: [CERN](https://videos.cern.ch/record/3021093)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

Reducing power consumption in FPGAs offers a range of benefits across various applications, including: extended battery life, simplified heat sink requirements, reduced complexity of the PCB power network, the potential for smaller package sizes, minimized heat-related measurement errors, and increased component longevity. Achieving energy-efficient FPGA design demands a comprehensive approach—from product strategy to the choice of process technology and on-chip architecture. In this talk, the speaker will provide an inside look at how Lattice FPGAs are engineered to deliver significant power savings..

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## Lectures

1. [Architecting FPGA for low power Leadership](https://invisiblenetwork.ai/learn/cern/3021093/3cbf5c19d7f1), 26 min (CERN's player)