# Application-Specific Arithmetic Operators with the FloPoCo HDL core generator

- Institution: CERN
- Department: FPGA Developers' Forum (FDF)
- Speaker: Florent de Dinechin
- Year: 2025
- Language: English
- Subjects: Mathematics
- Source: [CERN](https://videos.cern.ch/record/3021068)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

Software programming languages have trained us to view computing in terms of a handful of operations over a handful of integer and floating-point formats: those supported by general-purpose processors and GPUs. In FPGAs, however, we have the opportunity to design the arithmetic for the application. This is both a qualitative challenge (what is the best way to compute an exponential or an FFT in an FPGA?) and a quantitative one (how many bits are necessary and sufficient on each bus of the hardware?). Addressing these challenges has been the goal of the open-source FloPoCo project (www.flopoco.org) for 15 years. This talk will demonstrate some of its fancy operators, review some of the methodologies developed for optimizing and testing them, and discuss the challenges and opportunities of HLS in this context. It will also shamelessly advertise our recent book "Application-Specific Arithmetic: Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era"..

0:00:00 Slide 1

0:01:19 Slide 2

0:08:31 Slide 3

0:09:32 Slide 4

0:12:26 Slide 5

0:13:47 Slide 6

0:21:51 Slide 7

0:24:33 Slide 8

0:26:47 Slide 9

0:29:08 Slide 10

0:30:34 Slide 11

## Lectures

1. [Application-Specific Arithmetic Operators with the FloPoCo HDL core generator](https://invisiblenetwork.ai/learn/cern/3021068/34f3abd1c3c9), 33 min (CERN's player)