# FAST2: a new family of front-end ASICs to read out thin Ultra-Fast Silicon detectors achieving picosecond time resolution.

- Institution: CERN
- Department: Conferences
- Taught by: Marco Ferrero, Alejandro David Martinez Rojas
- Year: 2021
- Language: English
- Subjects: Physics, Engineering
- Source: [CERN](https://videos.cern.ch/record/3017885)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

We present the first results obtained with the FAST2 family of ASICs. The FAST2 ASIC family, designed in the 110 nm CMOS technology, has been optimized for the read-out of Ultra-Fast Silicon Detectors, aiming to achieve a combined total time resolution of less than 40 ps. In the FAST2 family, the ASIC (FAST2_A) presents 16 channels and has only the amplification stage with a timing jitter lower than 16 ps experimentally, and power dissipation of 1 mW/ch..

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## Lectures

1. [FAST2: a new family of front-end ASICs to read out thin Ultra-Fast Silicon detectors achieving picosecond time resolution.](https://invisiblenetwork.ai/learn/cern/3017885/ccf8f8124800), 17 min (CERN's player)