# Building a RISC-V CPU in 5 minutes

- Institution: CERN
- Department: IT Lightning Talks (ITLT)
- Speaker: James Devine
- Year: 2019
- Language: English
- Source: [CERN](https://videos.cern.ch/record/3010265)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Teens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

RISC-V is a fully open source processor architecture. It's rapidly being adopted by major tech companies as an alternative to ARM licenses. With the advent of the IceStorm toolchain for the Lattice iCE40 FPGA, it's now possible to construct your own RISC-V processor core and compile code to run on it using exclusively open source tools. This talk will include an overview of the RISC-V architecture, the toolchains for device synthesis and code compilation and will end with a very short demo of a working processor built during the talk!.

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## Lectures

1. [Building a RISC-V CPU in 5 minutes](https://invisiblenetwork.ai/learn/cern/3010265/183c83c24cd0), 9 min (CERN's player)